Defined in 7 files as a prototype:
- drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c, line 196 (as a prototype)
- drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c, line 220 (as a prototype)
- drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c, line 247 (as a prototype)
- drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c, line 212 (as a prototype)
- drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c, line 255 (as a prototype)
- drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c, line 264 (as a prototype)
- drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c, line 312 (as a prototype)
Defined in 8 files as a function:
- drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c, line 3082 (as a function)
- drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c, line 3156 (as a function)
- drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c, line 3166 (as a function)
- drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c, line 3221 (as a function)
- drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c, line 3534 (as a function)
- drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c, line 3640 (as a function)
- drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c, line 1954 (as a function)
- drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c, line 6547 (as a function)
Referenced in 8 files:
- drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
- drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
- drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
- drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
- drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
- drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
- drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
- drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
Smatch caller information:
5b3f9f3a27e33f8 dml_core_ms_prefetch_check() -> CalculateFlipSchedule()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | s | 4096-ptr_max |
| PARAM_VALUE | 0 | s->CalculateFlipSchedule_locals.Tr0_flip | -inf-1.797693e+308 |
| PARAM_VALUE | 0 | s->CalculateFlipSchedule_locals.Tvm_flip | -inf-1.797693e+308 |
| PARAM_VALUE | 0 | s->CalculateFlipSchedule_locals.dpte_row_bytes | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | s->CalculateFlipSchedule_locals.hvm_scaled_row_bytes | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | s->CalculateFlipSchedule_locals.hvm_scaled_vm_bytes | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | s->CalculateFlipSchedule_locals.hvm_scaled_vm_row_bytes | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | s->CalculateFlipSchedule_locals.lb_flip_bw | -inf-1.797693e+308 |
| PARAM_VALUE | 0 | s->CalculateFlipSchedule_locals.max_flip_time | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | s->CalculateFlipSchedule_locals.min_row_height | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | s->CalculateFlipSchedule_locals.min_row_height_chroma | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | s->CalculateFlipSchedule_locals.min_row_time | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | s->CalculateFlipSchedule_locals.num_rows | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | use_lb_flip_bw | 1 |
| PARAM_VALUE | 3 | HostVMInefficiencyFactor | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 9 | vm_bytes | 0.000000e+00-4.294967e+09 |
| PARAM_VALUE | 10 | DPTEBytesPerRow | 0.000000e+00-4.294967e+09 |
| PARAM_VALUE | 11 | BandwidthAvailableForImmediateFlip | -1.797693e+308-5.010421e-293 |
| PARAM_VALUE | 28 | dst_y_per_vm_flip | 4096-ptr_max |
| PARAM_VALUE | 29 | dst_y_per_row_flip | 4096-ptr_max |
| PARAM_VALUE | 30 | final_flip_bw | 4096-ptr_max |
| PARAM_VALUE | 31 | ImmediateFlipSupportedForPipe | 4096-ptr_max |
| CAPPED_DATA | 11 | BandwidthAvailableForImmediateFlip | 1 |
| CAPPED_DATA | 11 | BandwidthAvailableForImmediateFlip | 1 |
| DATA_SOURCE | 11 | BandwidthAvailableForImmediateFlip | r get_bandwidth_available_for_immediate_flip |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20v2.c dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation() -> CalculateFlipSchedule()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | s | 4096-ptr_max |
| PARAM_VALUE | 2 | use_lb_flip_bw | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 3 | HostVMInefficiencyFactor | 1-u32max |
| PARAM_VALUE | 5 | Tr0_trips_flip | -inf-inf |
| PARAM_VALUE | 9 | vm_bytes | 0.000000e+00-4.294967e+09 |
| PARAM_VALUE | 11 | BandwidthAvailableForImmediateFlip | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 19 | dpte_row_height_chroma | 4096-ptr_max |
| PARAM_VALUE | 19 | *dpte_row_height_chroma | 0.000000e+00-4.940656e-324 |
| PARAM_VALUE | 20 | use_one_row_for_frame_flip | 4096-ptr_max |
| PARAM_VALUE | 20 | *use_one_row_for_frame_flip | 0.000000e+00-4.940656e-324 |
| PARAM_VALUE | 21 | max_flip_time_us | 4096-ptr_max |
| PARAM_VALUE | 21 | *max_flip_time_us | 0.000000e+00-1.844674e+19 |
| PARAM_VALUE | 22 | max_flip_time_lines | 4096-ptr_max |
| CAPPED_DATA | 0 | s->vba.DCFCLKDeepSleep | 1 |
| CAPPED_DATA | 0 | s->vba.DISPCLKWithRamping | 1 |
| CAPPED_DATA | 0 | s->vba.DISPCLKWithRampingRoundedToDFSGranularity | 1 |
| CAPPED_DATA | 0 | s->vba.DISPCLKWithoutRamping | 1 |
| CAPPED_DATA | 0 | s->vba.DISPCLKWithoutRampingRoundedToDFSGranularity | 1 |
| CAPPED_DATA | 0 | s->vba.DISPCLK_calculated | 1 |
| CAPPED_DATA | 0 | s->vba.FabricAndDRAMBandwidth | 1 |
| CAPPED_DATA | 0 | s->vba.GlobalDPPCLK | 1 |
| CAPPED_DATA | 0 | s->vba.MaxDispclkRoundedToDFSGranularity | 1 |
| CAPPED_DATA | 0 | s->vba.MaxPSCLToLBThroughput | 1 |
| CAPPED_DATA | 0 | s->vba.MinFullDETBufferingTime | 1 |
| CAPPED_DATA | 0 | s->vba.MinUrgentLatencySupportUs | 1 |
| CAPPED_DATA | 0 | s->vba.NumberOfActivePlanes | 1 |
| CAPPED_DATA | 0 | s->vba.PartOfBurstThatFitsInROB | 1 |
| CAPPED_DATA | 0 | s->vba.ReturnBW | 1 |
| CAPPED_DATA | 0 | s->vba.ReturnBandwidthToDCN | 1 |
| CAPPED_DATA | 0 | s->vba.SmallestVBlank | 1 |
| CAPPED_DATA | 0 | s->vba.UrgentLatencyPixelDataOnly | 1 |
| CAPPED_DATA | 0 | s->vba.WritebackDISPCLK | 1 |
| CAPPED_DATA | 0 | s->vba.cache_num_pipes | 1 |
| CAPPED_DATA | 0 | s->vba.soc.num_states | 1 |
| CAPPED_DATA | 2 | use_lb_flip_bw | 1 |
| CAPPED_DATA | 2 | use_lb_flip_bw | 1 |
| DATA_SOURCE | 0 | s | $0 |
| PARAM_COMPARE | 0 | s->vba.DISPCLKWithRamping | <= $0->vba.WritebackDISPCLK |
| PARAM_COMPARE | 0 | s->vba.DISPCLKWithoutRamping | <= $0->vba.WritebackDISPCLK |
| BIT_INFO | 0 | s->vba.DCFCLKDeepSleep | 0x0,0x4020000000000000 |
| BIT_INFO | 0 | s->vba.VStartupLines | 0xc,0xffffffffffffffff |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| NO_OVERFLOW_SIMPLE | 0 | s->vba.cache_num_pipes |
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_mode_vba_30.c DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation() -> CalculateFlipSchedule()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | s | 4096-ptr_max |
| PARAM_VALUE | 2 | use_lb_flip_bw | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 3 | HostVMInefficiencyFactor | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 4 | Tvm_trips_flip | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 5 | Tr0_trips_flip | 1-u32max |
| PARAM_VALUE | 9 | vm_bytes | 0.000000e+00-4.294967e+09 |
| PARAM_VALUE | 13 | SourcePixelFormat | -inf-1.797693e+308 |
| PARAM_VALUE | 16 | VRatioChroma | 0.000000e+00-4.294967e+09 |
| PARAM_VALUE | 17 | Tno_bw_flip | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 18 | dpte_row_height | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 19 | dpte_row_height_chroma | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 25 | meta_row_height | 4096-ptr_max |
| PARAM_VALUE | 25 | *meta_row_height | 0.000000e+00-4.940656e-324 |
| PARAM_VALUE | 26 | meta_row_height_chroma | 4096-ptr_max |
| PARAM_VALUE | 26 | *meta_row_height_chroma | 0.000000e+00-4.940656e-324 |
| PARAM_VALUE | 27 | dcc_mrq_enable | 4096-ptr_max |
| PARAM_VALUE | 27 | *dcc_mrq_enable | -inf-inf |
| PARAM_VALUE | 28 | dst_y_per_vm_flip | 4096-ptr_max |
| CAPPED_DATA | 0 | s->vba.NumberOfActivePlanes | 1 |
| CAPPED_DATA | 0 | s->vba.cache_num_pipes | 1 |
| CAPPED_DATA | 0 | s->vba.soc.num_states | 1 |
| CAPPED_DATA | 4 | Tvm_trips_flip | 1 |
| CAPPED_DATA | 4 | Tvm_trips_flip | 1 |
| DATA_SOURCE | 0 | s | $0 |
| DATA_SOURCE | 3 | HostVMInefficiencyFactor | r CalculateExtraLatency |
| DATA_SOURCE | 4 | Tvm_trips_flip | r CalculateUrgentLatency |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| NO_OVERFLOW_SIMPLE | 0 | s->vba.cache_num_pipes |
drivers/gpu/drm/amd/amdgpu/../display/dc/dml2_0/display_mode_core.c dml_prefetch_check() -> CalculateFlipSchedule()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 1 | iflip_enable | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | use_lb_flip_bw | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 8 | GPUVMEnable | 0.000000e+00-4.294967e+09 |
| PARAM_VALUE | 9 | vm_bytes | 0.000000e+00-4.294967e+09 |
| PARAM_VALUE | 10 | DPTEBytesPerRow | 0.000000e+00-4.294967e+09 |
| PARAM_VALUE | 11 | BandwidthAvailableForImmediateFlip | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 14 | LineTime | 0.000000e+00-4.294967e+09 |
| PARAM_VALUE | 15 | VRatio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 16 | VRatioChroma | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 24 | meta_row_bytes | 4096-ptr_max |
| PARAM_VALUE | 25 | meta_row_height | 4096-ptr_max |
| PARAM_VALUE | 26 | meta_row_height_chroma | 4096-ptr_max |
| PARAM_VALUE | 27 | dcc_mrq_enable | 4096-ptr_max |
| DATA_SOURCE | 1 | iflip_enable | r CalculateExtraLatency |
| DATA_SOURCE | 11 | BandwidthAvailableForImmediateFlip | r CalculateBandwidthAvailableForImmediateFlip |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20.c dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation() -> CalculateFlipSchedule()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | s | 4096-ptr_max |
| PARAM_VALUE | 2 | use_lb_flip_bw | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 3 | HostVMInefficiencyFactor | 1-u32max |
| PARAM_VALUE | 5 | Tr0_trips_flip | -inf-inf |
| PARAM_VALUE | 9 | vm_bytes | 0.000000e+00-4.294967e+09 |
| PARAM_VALUE | 11 | BandwidthAvailableForImmediateFlip | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 19 | dpte_row_height_chroma | 4096-ptr_max |
| PARAM_VALUE | 19 | *dpte_row_height_chroma | 0.000000e+00-4.940656e-324 |
| PARAM_VALUE | 20 | use_one_row_for_frame_flip | 4096-ptr_max |
| PARAM_VALUE | 20 | *use_one_row_for_frame_flip | 0.000000e+00-4.940656e-324 |
| PARAM_VALUE | 21 | max_flip_time_us | 4096-ptr_max |
| PARAM_VALUE | 21 | *max_flip_time_us | 0.000000e+00-1.844674e+19 |
| PARAM_VALUE | 22 | max_flip_time_lines | 4096-ptr_max |
| CAPPED_DATA | 0 | s->vba.DCFCLKDeepSleep | 1 |
| CAPPED_DATA | 0 | s->vba.DISPCLKWithRamping | 1 |
| CAPPED_DATA | 0 | s->vba.DISPCLKWithRampingRoundedToDFSGranularity | 1 |
| CAPPED_DATA | 0 | s->vba.DISPCLKWithoutRamping | 1 |
| CAPPED_DATA | 0 | s->vba.DISPCLKWithoutRampingRoundedToDFSGranularity | 1 |
| CAPPED_DATA | 0 | s->vba.DISPCLK_calculated | 1 |
| CAPPED_DATA | 0 | s->vba.FabricAndDRAMBandwidth | 1 |
| CAPPED_DATA | 0 | s->vba.GlobalDPPCLK | 1 |
| CAPPED_DATA | 0 | s->vba.LastPixelOfLineExtraWatermark | 1 |
| CAPPED_DATA | 0 | s->vba.MaxDispclkRoundedToDFSGranularity | 1 |
| CAPPED_DATA | 0 | s->vba.MaxPSCLToLBThroughput | 1 |
| CAPPED_DATA | 0 | s->vba.MinFullDETBufferingTime | 1 |
| CAPPED_DATA | 0 | s->vba.MinUrgentLatencySupportUs | 1 |
| CAPPED_DATA | 0 | s->vba.NumberOfActivePlanes | 1 |
| CAPPED_DATA | 0 | s->vba.PartOfBurstThatFitsInROB | 1 |
| CAPPED_DATA | 0 | s->vba.ReturnBW | 1 |
| CAPPED_DATA | 0 | s->vba.ReturnBandwidthToDCN | 1 |
| CAPPED_DATA | 0 | s->vba.SmallestVBlank | 1 |
| CAPPED_DATA | 0 | s->vba.WritebackDISPCLK | 1 |
| CAPPED_DATA | 0 | s->vba.cache_num_pipes | 1 |
| CAPPED_DATA | 0 | s->vba.soc.num_states | 1 |
| DATA_SOURCE | 0 | s | $0 |
| PARAM_COMPARE | 0 | s->vba.DISPCLKWithRamping | <= $0->vba.WritebackDISPCLK |
| PARAM_COMPARE | 0 | s->vba.DISPCLKWithoutRamping | <= $0->vba.WritebackDISPCLK |
| BIT_INFO | 0 | s->vba.DCFCLKDeepSleep | 0x0,0x4020000000000000 |
| BIT_INFO | 0 | s->vba.VStartupLines | 0xc,0xffffffffffffffff |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| NO_OVERFLOW_SIMPLE | 0 | s->vba.cache_num_pipes |
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20.c dml20_ModeSupportAndSystemConfigurationFull() -> CalculateFlipSchedule()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | s | 4096-ptr_max |
| PARAM_VALUE | 2 | use_lb_flip_bw | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 3 | HostVMInefficiencyFactor | 1-u32max |
| PARAM_VALUE | 4 | Tvm_trips_flip | 0 |
| PARAM_VALUE | 9 | vm_bytes | 0.000000e+00-4.294967e+09 |
| PARAM_VALUE | 11 | BandwidthAvailableForImmediateFlip | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 19 | dpte_row_height_chroma | 4096-ptr_max |
| PARAM_VALUE | 19 | *dpte_row_height_chroma | 0.000000e+00-4.940656e-324 |
| PARAM_VALUE | 20 | use_one_row_for_frame_flip | 4096-ptr_max |
| PARAM_VALUE | 20 | *use_one_row_for_frame_flip | 0.000000e+00-4.940656e-324 |
| PARAM_VALUE | 21 | max_flip_time_us | 4096-ptr_max |
| PARAM_VALUE | 21 | *max_flip_time_us | -inf-inf |
| PARAM_VALUE | 22 | max_flip_time_lines | 4096-ptr_max |
| CAPPED_DATA | 0 | s->vba.MaxDispclkRoundedDownToDFSGranularity | 1 |
| CAPPED_DATA | 0 | s->vba.MaxDppclkRoundedDownToDFSGranularity | 1 |
| CAPPED_DATA | 0 | s->vba.MaxHSCLRatio | 1 |
| CAPPED_DATA | 0 | s->vba.MaxPrefetchMode | 1 |
| CAPPED_DATA | 0 | s->vba.MaxVSCLRatio | 1 |
| CAPPED_DATA | 0 | s->vba.MaximumSwathWidthInDETBuffer | 1 |
| CAPPED_DATA | 0 | s->vba.MaximumSwathWidthInLineBuffer | 1 |
| CAPPED_DATA | 0 | s->vba.NextPrefetchMode | 1 |
| CAPPED_DATA | 0 | s->vba.PlaneRequiredDISPCLK | 1 |
| CAPPED_DATA | 0 | s->vba.SREnterPlusExitTime | 1 |
| CAPPED_DATA | 0 | s->vba.TWait | 1 |
| CAPPED_DATA | 0 | s->vba.TotalDSCUnitsRequired | 1 |
| CAPPED_DATA | 0 | s->vba.TotalNumberOfActiveOTG | 1 |
| CAPPED_DATA | 0 | s->vba.TotalNumberOfActiveWriteback | 1 |
| CAPPED_DATA | 0 | s->vba.UrgentLatency | 1 |
| CAPPED_DATA | 0 | s->vba.WritebackMaxHSCLRatio | 1 |
| CAPPED_DATA | 0 | s->vba.WritebackMaxVSCLRatio | 1 |
| CAPPED_DATA | 0 | s->vba.WritebackMinHSCLRatio | 1 |
| CAPPED_DATA | 0 | s->vba.WritebackMinVSCLRatio | 1 |
| CAPPED_DATA | 0 | s->vba.soc.num_states | 1 |
| DATA_SOURCE | 0 | s | $0 |
| PARAM_COMPARE | 0 | s->vba.MaxNumOTG | <= $0->vba.TotalNumberOfActiveOTG |
| PARAM_COMPARE | 0 | s->vba.MaximumSwathWidthInDETBuffer | >= $0->vba.MaximumSwathWidthInLineBuffer |
| PARAM_COMPARE | 0 | s->vba.NumberOfDSC | <= $0->vba.TotalDSCUnitsRequired |
| PARAM_COMPARE | 0 | s->vba.SREnterPlusExitTime | <= $0->vba.UrgentLatency |
| BIT_INFO | 0 | s->vba.MaximumSwathWidthSupport | 0x4080000000000000,0xffffffffffffffff |
| BIT_INFO | 0 | s->vba.PDEAndMetaPTEBytesPerFrameC | 0x0,0xffffffff |
| BIT_INFO | 0 | s->vba.PDEAndMetaPTEBytesPerFrameY | 0x0,0xffffffff |
| BIT_INFO | 0 | s->vba.TotalNumberOfActiveOTG | 0x0,0x7fffffffffffffff |
| BIT_INFO | 0 | s->vba.slices | 0x0,0xf |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| NO_OVERFLOW_SIMPLE | 0 | s->vba.cache_num_pipes |
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_mode_vba_21.c DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation() -> CalculateFlipSchedule()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | s | 4096-ptr_max |
| PARAM_VALUE | 2 | use_lb_flip_bw | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 3 | HostVMInefficiencyFactor | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 4 | Tvm_trips_flip | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 5 | Tr0_trips_flip | 1-u32max |
| PARAM_VALUE | 7 | Tr0_trips_flip_rounded | 1-u32max |
| PARAM_VALUE | 16 | VRatioChroma | 0.000000e+00-4.294967e+09 |
| PARAM_VALUE | 17 | Tno_bw_flip | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 18 | dpte_row_height | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 24 | meta_row_bytes | 4096-ptr_max |
| PARAM_VALUE | 24 | *meta_row_bytes | 0.000000e+00-4.940656e-324 |
| PARAM_VALUE | 25 | meta_row_height | 4096-ptr_max |
| PARAM_VALUE | 25 | *meta_row_height | 0.000000e+00-4.940656e-324 |
| PARAM_VALUE | 26 | meta_row_height_chroma | 4096-ptr_max |
| PARAM_VALUE | 26 | *meta_row_height_chroma | -inf-inf |
| PARAM_VALUE | 27 | dcc_mrq_enable | 4096-ptr_max |
| CAPPED_DATA | 0 | s->vba.DISPCLKWithRamping | 1 |
| CAPPED_DATA | 0 | s->vba.DISPCLKWithRampingRoundedToDFSGranularity | 1 |
| CAPPED_DATA | 0 | s->vba.DISPCLKWithoutRamping | 1 |
| CAPPED_DATA | 0 | s->vba.DISPCLKWithoutRampingRoundedToDFSGranularity | 1 |
| CAPPED_DATA | 0 | s->vba.DISPCLK_calculated | 1 |
| CAPPED_DATA | 0 | s->vba.FractionOfUrgentBandwidth | 1 |
| CAPPED_DATA | 0 | s->vba.GlobalDPPCLK | 1 |
| CAPPED_DATA | 0 | s->vba.MaxDispclkRoundedToDFSGranularity | 1 |
| CAPPED_DATA | 0 | s->vba.MaxPSCLToLBThroughput | 1 |
| CAPPED_DATA | 0 | s->vba.NumberOfActivePlanes | 1 |
| CAPPED_DATA | 0 | s->vba.ReturnBW | 1 |
| CAPPED_DATA | 0 | s->vba.UrgentLatency | 1 |
| CAPPED_DATA | 0 | s->vba.UrgentLatencyPixelDataOnly | 1 |
| CAPPED_DATA | 0 | s->vba.UrgentLatencyPixelMixedWithVMData | 1 |
| CAPPED_DATA | 0 | s->vba.UrgentLatencyVMDataOnly | 1 |
| CAPPED_DATA | 0 | s->vba.UrgentOutOfOrderReturnPerChannel | 1 |
| CAPPED_DATA | 0 | s->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly | 1 |
| CAPPED_DATA | 0 | s->vba.UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData | 1 |
| CAPPED_DATA | 0 | s->vba.UrgentOutOfOrderReturnPerChannelVMDataOnly | 1 |
| CAPPED_DATA | 0 | s->vba.WritebackDISPCLK | 1 |
| CAPPED_DATA | 0 | s->vba.cache_num_pipes | 1 |
| CAPPED_DATA | 0 | s->vba.soc.num_states | 1 |
| CAPPED_DATA | 4 | Tvm_trips_flip | 1 |
| CAPPED_DATA | 4 | Tvm_trips_flip | 1 |
| DATA_SOURCE | 0 | s | $0 |
| DATA_SOURCE | 3 | HostVMInefficiencyFactor | r CalculateExtraLatency |
| DATA_SOURCE | 4 | Tvm_trips_flip | r dml_max3 |
| PARAM_COMPARE | 0 | s->vba.DISPCLKWithRamping | <= $0->vba.WritebackDISPCLK |
| PARAM_COMPARE | 0 | s->vba.DISPCLKWithoutRamping | <= $0->vba.WritebackDISPCLK |
| PARAM_COMPARE | 0 | s->vba.UrgentLatencyPixelDataOnly | <= $0->vba.UrgentLatencyPixelMixedWithVMData |
| PARAM_COMPARE | 0 | s->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly | <= $0->vba.UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData |
| BIT_INFO | 0 | s->vba.VStartupLines | 0xc,0xffffffffffffffff |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| NO_OVERFLOW_SIMPLE | 0 | s->vba.cache_num_pipes |
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_mode_vba_21.c dml21_ModeSupportAndSystemConfigurationFull() -> CalculateFlipSchedule()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | s | 4096-ptr_max |
| PARAM_VALUE | 2 | use_lb_flip_bw | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 3 | HostVMInefficiencyFactor | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 4 | Tvm_trips_flip | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 5 | Tr0_trips_flip | 1-u32max |
| PARAM_VALUE | 7 | Tr0_trips_flip_rounded | 1-u32max |
| PARAM_VALUE | 16 | VRatioChroma | 0.000000e+00-4.294967e+09 |
| PARAM_VALUE | 18 | dpte_row_height | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 24 | meta_row_bytes | 4096-ptr_max |
| PARAM_VALUE | 24 | *meta_row_bytes | 0.000000e+00-4.940656e-324 |
| PARAM_VALUE | 25 | meta_row_height | 4096-ptr_max |
| PARAM_VALUE | 25 | *meta_row_height | 0.000000e+00-4.940656e-324 |
| PARAM_VALUE | 26 | meta_row_height_chroma | 4096-ptr_max |
| PARAM_VALUE | 26 | *meta_row_height_chroma | -inf-inf |
| PARAM_VALUE | 27 | dcc_mrq_enable | 4096-ptr_max |
| CAPPED_DATA | 0 | s->vba.MaxDispclkRoundedDownToDFSGranularity | 1 |
| CAPPED_DATA | 0 | s->vba.MaxDppclkRoundedDownToDFSGranularity | 1 |
| CAPPED_DATA | 0 | s->vba.MaxHSCLRatio | 1 |
| CAPPED_DATA | 0 | s->vba.MaxPrefetchMode | 1 |
| CAPPED_DATA | 0 | s->vba.MaxVSCLRatio | 1 |
| CAPPED_DATA | 0 | s->vba.MaxVStartup | 1 |
| CAPPED_DATA | 0 | s->vba.MaximumReadBandwidthWithPrefetch | 1 |
| CAPPED_DATA | 0 | s->vba.MaximumSwathWidthInDETBuffer | 1 |
| CAPPED_DATA | 0 | s->vba.MaximumSwathWidthInLineBuffer | 1 |
| CAPPED_DATA | 0 | s->vba.MaximumSwathWidthSupport | 1 |
| CAPPED_DATA | 0 | s->vba.NextPrefetchMode | 1 |
| CAPPED_DATA | 0 | s->vba.NumberOfActivePlanes | 1 |
| CAPPED_DATA | 0 | s->vba.PlaneRequiredDISPCLK | 1 |
| CAPPED_DATA | 0 | s->vba.SREnterPlusExitTime | 1 |
| CAPPED_DATA | 0 | s->vba.TWait | 1 |
| CAPPED_DATA | 0 | s->vba.TotalDSCUnitsRequired | 1 |
| CAPPED_DATA | 0 | s->vba.TotalNumberOfActiveWriteback | 1 |
| CAPPED_DATA | 0 | s->vba.UrgentLatency | 1 |
| CAPPED_DATA | 0 | s->vba.UrgentLatencyPixelDataOnly | 1 |
| CAPPED_DATA | 0 | s->vba.UrgentLatencyPixelMixedWithVMData | 1 |
| CAPPED_DATA | 0 | s->vba.UrgentLatencyVMDataOnly | 1 |
| CAPPED_DATA | 0 | s->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly | 1 |
| CAPPED_DATA | 0 | s->vba.UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData | 1 |
| CAPPED_DATA | 0 | s->vba.UrgentOutOfOrderReturnPerChannelVMDataOnly | 1 |
| CAPPED_DATA | 0 | s->vba.WritebackMaxHSCLRatio | 1 |
| CAPPED_DATA | 0 | s->vba.WritebackMaxVSCLRatio | 1 |
| CAPPED_DATA | 0 | s->vba.WritebackMinHSCLRatio | 1 |
| CAPPED_DATA | 0 | s->vba.WritebackMinVSCLRatio | 1 |
| CAPPED_DATA | 0 | s->vba.soc.num_states | 1 |
| CAPPED_DATA | 4 | Tvm_trips_flip | 1 |
| CAPPED_DATA | 4 | Tvm_trips_flip | 1 |
| DATA_SOURCE | 0 | s | $0 |
| DATA_SOURCE | 3 | HostVMInefficiencyFactor | r CalculateExtraLatency |
| DATA_SOURCE | 4 | Tvm_trips_flip | r dml_max3 |
| PARAM_COMPARE | 0 | s->vba.MaxNumOTG | <= $0->vba.TotalNumberOfActiveOTG |
| PARAM_COMPARE | 0 | s->vba.MaximumSwathWidthInDETBuffer | >= $0->vba.MaximumSwathWidthInLineBuffer |
| PARAM_COMPARE | 0 | s->vba.NumberOfDSC | <= $0->vba.TotalDSCUnitsRequired |
| PARAM_COMPARE | 0 | s->vba.SREnterPlusExitTime | <= $0->vba.UrgentLatency |
| PARAM_COMPARE | 0 | s->vba.UrgentLatencyPixelDataOnly | <= $0->vba.UrgentLatencyPixelMixedWithVMData |
| PARAM_COMPARE | 0 | s->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly | <= $0->vba.UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData |
| PARAM_COMPARE | 4 | Tvm_trips_flip | >= $0->vba.SREnterPlusExitTime |
| BIT_INFO | 0 | s->vba.MaximumSwathWidthSupport | 0x4080000000000000,0xffffffffffffffff |
| BIT_INFO | 0 | s->vba.PDEAndMetaPTEBytesPerFrameC | 0x0,0xffffffff |
| BIT_INFO | 0 | s->vba.PDEAndMetaPTEBytesPerFrameY | 0x0,0xffffffff |
| BIT_INFO | 0 | s->vba.slices | 0x0,0xf |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| NO_OVERFLOW_SIMPLE | 0 | s->vba.cache_num_pipes |
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_mode_vba_31.c DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation() -> CalculateFlipSchedule()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | s | 4096-ptr_max |
| PARAM_VALUE | 2 | use_lb_flip_bw | -1.797693e+308-inf |
| PARAM_VALUE | 3 | HostVMInefficiencyFactor | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 4 | Tvm_trips_flip | -1.797693e+308-1.797693e+308 |
| CAPPED_DATA | 0 | s->vba.NumberOfActivePlanes | 1 |
| CAPPED_DATA | 0 | s->vba.cache_num_pipes | 1 |
| CAPPED_DATA | 0 | s->vba.soc.num_states | 1 |
| CAPPED_DATA | 1 | iflip_enable | 1 |
| CAPPED_DATA | 2 | use_lb_flip_bw | 1 |
| CAPPED_DATA | 2 | use_lb_flip_bw | 1 |
| CAPPED_DATA | 4 | Tvm_trips_flip | 1 |
| CAPPED_DATA | 4 | Tvm_trips_flip | 1 |
| DATA_SOURCE | 0 | s | $0 |
| DATA_SOURCE | 3 | HostVMInefficiencyFactor | r CalculateExtraLatency |
| DATA_SOURCE | 4 | Tvm_trips_flip | r CalculateUrgentLatency |
| FUZZY_MAX | 2 | use_lb_flip_bw | 1.000000e+00 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| NO_OVERFLOW_SIMPLE | 0 | s->vba.cache_num_pipes |
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_mode_vba_314.c DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation() -> CalculateFlipSchedule()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | s | 4096-ptr_max |
| PARAM_VALUE | 2 | use_lb_flip_bw | -1.797693e+308-inf |
| PARAM_VALUE | 3 | HostVMInefficiencyFactor | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 4 | Tvm_trips_flip | -1.797693e+308-1.797693e+308 |
| CAPPED_DATA | 0 | s->vba.NumberOfActivePlanes | 1 |
| CAPPED_DATA | 0 | s->vba.cache_num_pipes | 1 |
| CAPPED_DATA | 0 | s->vba.soc.num_states | 1 |
| CAPPED_DATA | 1 | iflip_enable | 1 |
| CAPPED_DATA | 2 | use_lb_flip_bw | 1 |
| CAPPED_DATA | 2 | use_lb_flip_bw | 1 |
| CAPPED_DATA | 4 | Tvm_trips_flip | 1 |
| CAPPED_DATA | 4 | Tvm_trips_flip | 1 |
| DATA_SOURCE | 0 | s | $0 |
| DATA_SOURCE | 3 | HostVMInefficiencyFactor | r CalculateExtraLatency |
| DATA_SOURCE | 4 | Tvm_trips_flip | r CalculateUrgentLatency |
| FUZZY_MAX | 2 | use_lb_flip_bw | 1.000000e+00 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| NO_OVERFLOW_SIMPLE | 0 | s->vba.cache_num_pipes |