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Documented in 1 files:

Defined in 1 files as a prototype:

Defined in 1 files as a function:

Referenced in 5 files:

Smatch caller information:

19f4aff6129bc862 gfx_v9_0_ring_begin_use_compute() -> amdgpu_gfx_enforce_isolation_ring_begin_use()

Type Parameter Key Value
PARAM_VALUE 0 ring 4096-ptr_max
PARAM_VALUE 0 ring->adev 4096-ptr_max
PARAM_VALUE 0 ring->adev->gfx.rlc.cs_data->section->reg_index 0,4,40960,41022,41164,41174,41176,41179,41461,41471-41472,41530,41630,41632-41633,41635,41637-41638,41694,41701,41717,41920,62460,65472
PARAM_VALUE 0 ring->adev->gfx.rlc.reg_funcs->rreg32 4096-ptr_max
PARAM_VALUE 0 ring->adev->mes.funcs->reset_hw_queue 4096-ptr_max
PARAM_VALUE 0 ring->adev->mman.bdev.dev_mapping->i_mmap_rwsem.first_waiter->handoff_set 0-1
PARAM_VALUE 0 ring->adev->mman.bdev.dev_mapping->i_mmap_rwsem.first_waiter->type 0-1
PARAM_VALUE 0 ring->adev->reset_domain->sem.first_waiter->handoff_set 0-1
PARAM_VALUE 0 ring->adev->reset_domain->sem.first_waiter->type 0-1
PARAM_VALUE 0 ring->funcs 4096-ptr_max
PARAM_VALUE 0 ring->funcs->begin_use 1-u64max
BUF_SIZE 0 ring (-1),1360,2720,4080,13600,21760,85680,87040
BUF_SIZE 0 ring (-1),1360,2720,4080,13600,21760,85680,87040
CAPPED_DATA 0 ring->count_dw 1
DATA_SOURCE 0 ring $0
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HOST_DATA 0 ring->count_dw 0-s32max[c]
HOST_DATA 0 ring->wptr 0-u32max
HOST_DATA 0 ring->wptr_old 0-u32max
HALF_LOCKED2 &adev->gfx.gpu_clock_mutex
HALF_LOCKED2 &adev->reset_domain->sem
HALF_LOCKED2 &adev->srbm_mutex
HALF_LOCKED2 &kiq->ring_lock
HALF_LOCKED2 &mux->lock
HALF_LOCKED2 &pool->lock
HALF_LOCKED2 flags
HALF_LOCKED2 global &drm_unplug_srcu
HALF_LOCKED2 ring_lock

2424e8ec9bf51854 gfx_v12_0_ring_begin_use() -> amdgpu_gfx_enforce_isolation_ring_begin_use()

Type Parameter Key Value
PARAM_VALUE 0 ring 4096-ptr_max
PARAM_VALUE 0 ring->adev 4096-ptr_max
PARAM_VALUE 0 ring->adev->gfx.rlc.cs_data->section->reg_index 0,4,40960,41022,41164,41174,41176,41179,41461,41471-41472,41530,41630,41632-41633,41635,41637-41638,41694,41701,41717,41920,62460,65472
PARAM_VALUE 0 ring->adev->gfx.rlc.reg_funcs->rreg32 4096-ptr_max
PARAM_VALUE 0 ring->adev->mes.funcs->reset_hw_queue 4096-ptr_max
PARAM_VALUE 0 ring->adev->mman.bdev.dev_mapping->i_mmap_rwsem.first_waiter->handoff_set 0-1
PARAM_VALUE 0 ring->adev->mman.bdev.dev_mapping->i_mmap_rwsem.first_waiter->type 0-1
PARAM_VALUE 0 ring->adev->reset_domain->sem.first_waiter->handoff_set 0-1
PARAM_VALUE 0 ring->adev->reset_domain->sem.first_waiter->type 0-1
PARAM_VALUE 0 ring->funcs 4096-ptr_max
PARAM_VALUE 0 ring->funcs->begin_use 1-u64max
BUF_SIZE 0 ring (-1),1360,2720,4080,13600,21760,85680,87040
BUF_SIZE 0 ring (-1),1360,2720,4080,13600,21760,85680,87040
CAPPED_DATA 0 ring->adev 1
CAPPED_DATA 0 ring->count_dw 1
DATA_SOURCE 0 ring $0
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HOST_DATA 0 ring->count_dw 0-s32max[c]
HOST_DATA 0 ring->wptr 0-u32max
HOST_DATA 0 ring->wptr_old 0-u32max
HALF_LOCKED2 &adev->gfx.gpu_clock_mutex
HALF_LOCKED2 &adev->reset_domain->sem
HALF_LOCKED2 &adev->srbm_mutex
HALF_LOCKED2 &kiq->ring_lock
HALF_LOCKED2 &mux->lock
HALF_LOCKED2 &pool->lock
HALF_LOCKED2 flags
HALF_LOCKED2 global &drm_unplug_srcu
HALF_LOCKED2 ring_lock

28ad57647bf6154f gfx_v11_0_ring_begin_use() -> amdgpu_gfx_enforce_isolation_ring_begin_use()

Type Parameter Key Value
PARAM_VALUE 0 ring 4096-ptr_max
PARAM_VALUE 0 ring->adev 4096-ptr_max
PARAM_VALUE 0 ring->adev->gfx.rlc.cs_data->section->reg_index 0,4,40960,41022,41164,41174,41176,41179,41461,41471-41472,41530,41630,41632-41633,41635,41637-41638,41694,41701,41717,41920,62460,65472
PARAM_VALUE 0 ring->adev->gfx.rlc.reg_funcs->rreg32 4096-ptr_max
PARAM_VALUE 0 ring->adev->mes.funcs->reset_hw_queue 4096-ptr_max
PARAM_VALUE 0 ring->adev->mman.bdev.dev_mapping->i_mmap_rwsem.first_waiter->handoff_set 0-1
PARAM_VALUE 0 ring->adev->mman.bdev.dev_mapping->i_mmap_rwsem.first_waiter->type 0-1
PARAM_VALUE 0 ring->adev->reset_domain->sem.first_waiter->handoff_set 0-1
PARAM_VALUE 0 ring->adev->reset_domain->sem.first_waiter->type 0-1
PARAM_VALUE 0 ring->funcs 4096-ptr_max
PARAM_VALUE 0 ring->funcs->begin_use 1-u64max
BUF_SIZE 0 ring (-1),1360,2720,4080,13600,21760,85680,87040
BUF_SIZE 0 ring (-1),1360,2720,4080,13600,21760,85680,87040
CAPPED_DATA 0 ring->adev 1
CAPPED_DATA 0 ring->count_dw 1
DATA_SOURCE 0 ring $0
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HOST_DATA 0 ring->count_dw 0-s32max[c]
HOST_DATA 0 ring->wptr 0-u32max
HOST_DATA 0 ring->wptr_old 0-u32max
HALF_LOCKED2 &adev->gfx.gpu_clock_mutex
HALF_LOCKED2 &adev->reset_domain->sem
HALF_LOCKED2 &adev->srbm_mutex
HALF_LOCKED2 &kiq->ring_lock
HALF_LOCKED2 &mux->lock
HALF_LOCKED2 &pool->lock
HALF_LOCKED2 flags
HALF_LOCKED2 global &drm_unplug_srcu
HALF_LOCKED2 ring_lock

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c gfx_v10_0_ring_begin_use() -> amdgpu_gfx_enforce_isolation_ring_begin_use()

Type Parameter Key Value
PARAM_VALUE 0 ring 4096-ptr_max
PARAM_VALUE 0 ring->adev 4096-ptr_max
PARAM_VALUE 0 ring->adev->gfx.rlc.cs_data->section->reg_index 0,4,40960,41022,41164,41174,41176,41179,41461,41471-41472,41530,41630,41632-41633,41635,41637-41638,41694,41701,41717,41920,62460,65472
PARAM_VALUE 0 ring->adev->gfx.rlc.reg_funcs->rreg32 4096-ptr_max
PARAM_VALUE 0 ring->adev->mes.funcs->reset_hw_queue 4096-ptr_max
PARAM_VALUE 0 ring->adev->mman.bdev.dev_mapping->i_mmap_rwsem.first_waiter->handoff_set 0-1
PARAM_VALUE 0 ring->adev->mman.bdev.dev_mapping->i_mmap_rwsem.first_waiter->type 0-1
PARAM_VALUE 0 ring->adev->reset_domain->sem.first_waiter->handoff_set 0-1
PARAM_VALUE 0 ring->adev->reset_domain->sem.first_waiter->type 0-1
PARAM_VALUE 0 ring->funcs 4096-ptr_max
PARAM_VALUE 0 ring->funcs->begin_use 1-u64max
BUF_SIZE 0 ring (-1),1360,2720,4080,13600,21760,85680,87040
BUF_SIZE 0 ring (-1),1360,2720,4080,13600,21760,85680,87040
CAPPED_DATA 0 ring->adev 1
CAPPED_DATA 0 ring->count_dw 1
DATA_SOURCE 0 ring $0
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HOST_DATA 0 ring->count_dw 0-s32max[c]
HOST_DATA 0 ring->wptr 0-u32max
HOST_DATA 0 ring->wptr_old 0-u32max
HALF_LOCKED2 &adev->gfx.gpu_clock_mutex
HALF_LOCKED2 &adev->reset_domain->sem
HALF_LOCKED2 &adev->srbm_mutex
HALF_LOCKED2 &kiq->ring_lock
HALF_LOCKED2 &mux->lock
HALF_LOCKED2 &pool->lock
HALF_LOCKED2 flags
HALF_LOCKED2 global &drm_unplug_srcu
HALF_LOCKED2 ring_lock

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c amdgpu_ring_alloc() -> (struct amdgpu_ring_funcs)->begin_use()

Type Parameter Key Value
PARAM_VALUE 0 ring 4096-ptr_max
PARAM_VALUE 0 ring->adev->gfx.rlc.cs_data->section->reg_index 0,4,40960,41022,41164,41174,41176,41179,41461,41471-41472,41530,41630,41632-41633,41635,41637-41638,41694,41701,41717,41920,62460,65472
PARAM_VALUE 0 ring->adev->gfx.rlc.reg_funcs->rreg32 4096-ptr_max
PARAM_VALUE 0 ring->adev->mes.funcs->reset_hw_queue 4096-ptr_max
PARAM_VALUE 0 ring->adev->reset_domain->sem.first_waiter->handoff_set 0-1
PARAM_VALUE 0 ring->adev->reset_domain->sem.first_waiter->type 0-1
PARAM_VALUE 0 ring->funcs 4096-ptr_max
PARAM_VALUE 0 ring->funcs->begin_use 1-u64max
BUF_SIZE 0 ring (-1),1360,2720,4080,13600,21760,87040
BUF_SIZE 0 ring (-1),1360,2720,4080,13600,21760,87040
CAPPED_DATA 0 ring->count_dw 1
DATA_SOURCE 0 ring $0
CONTAINER 0 -176-8+0 $(-1)
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HOST_DATA 0 ring->count_dw 0-s32max[c]
HOST_DATA 0 ring->wptr 0-u32max
HOST_DATA 0 ring->wptr_old 0-u32max
HALF_LOCKED2 &adev->reset_domain->sem
HALF_LOCKED2 &adev->srbm_mutex
HALF_LOCKED2 &kiq->ring_lock
HALF_LOCKED2 &mux->lock
HALF_LOCKED2 flags
HALF_LOCKED2 global &drm_unplug_srcu
HALF_LOCKED2 ring_lock