Defined in 1 files as a prototype:
Defined in 1 files as a function:
Referenced in 8 files:
- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c, line 4943
- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c, line 1852
- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c, line 1540
- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c, line 1511
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c, line 4407
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c, line 1998
- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c, line 2395
- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c, line 1047
Smatch caller information:
19f4aff6129bc862 gfx_v9_0_sw_init() -> amdgpu_gfx_is_mec_queue_enabled()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 0 | adev->gfx.mec.num_pipe_per_mec | 4 |
| PARAM_VALUE | 0 | adev->gfx.mec.num_queue_per_pipe | 8 |
| PARAM_VALUE | 1 | xcc_id | 0 |
| PARAM_VALUE | 2 | mec | 0-s32max |
| PARAM_VALUE | 3 | pipe | 0-3 |
| PARAM_VALUE | 4 | queue | 0-7 |
| BUF_SIZE | 0 | adev->gfx.cleaner_shader_ptr | (-1),304 |
| CAPPED_DATA | 0 | adev->gfx.num_gfx_rings | 1 |
| CAPPED_DATA | 2 | mec | 1 |
| FUZZY_MAX | 2 | mec | 0 |
| FUZZY_MAX | 3 | pipe | 3 |
| FUZZY_MAX | 4 | queue | 7 |
| PARAM_COMPARE | 0 | adev->gfx.mec.num_mec | > $2 |
| PARAM_COMPARE | 0 | adev->gfx.mec.num_pipe_per_mec | > $3 |
| PARAM_COMPARE | 0 | adev->gfx.mec.num_queue_per_pipe | > $4 |
| PARAM_COMPARE | 2 | mec | < $0->gfx.mec.num_mec |
| PARAM_COMPARE | 3 | pipe | < $0->gfx.mec.num_pipe_per_mec |
| PARAM_COMPARE | 4 | queue | < $0->gfx.mec.num_queue_per_pipe |
| HARD_MAX | 3 | pipe | 3 |
| HARD_MAX | 4 | queue | 7 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.bad_op_irq.num_types | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.cp_ecc_error_irq.num_types | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.eop_irq.num_types | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.mec.hpd_eop_obj->tbo.ttm->dma_ttm.sg->orig_nents | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.mec.mec_fw_obj->tbo.ttm->dma_ttm.sg->orig_nents | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.muxer.ring_entry_size | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.priv_inst_irq.num_types | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.priv_reg_irq.num_types | |
| UNITS | 2 | mec | unit_array_size |
| HALF_LOCKED2 | &pool->lock |
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c gfx_v9_4_3_sw_init() -> amdgpu_gfx_is_mec_queue_enabled()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 0 | adev->gfx.mec.num_pipe_per_mec | 1-u32max |
| PARAM_VALUE | 0 | adev->gfx.mec.num_queue_per_pipe | 1-u32max |
| PARAM_VALUE | 1 | xcc_id | 0-15 |
| PARAM_VALUE | 2 | mec | 0-s32max |
| PARAM_VALUE | 3 | pipe | 0-s32max |
| PARAM_VALUE | 4 | queue | 0-s32max |
| BUF_SIZE | 0 | adev->gfx.cleaner_shader_ptr | (-1),304 |
| CAPPED_DATA | 1 | xcc_id | 1 |
| CAPPED_DATA | 2 | mec | 1 |
| CAPPED_DATA | 3 | pipe | 1 |
| CAPPED_DATA | 4 | queue | 1 |
| FUZZY_MAX | 0 | adev->gfx.mec.num_queue_per_pipe | 8 |
| FUZZY_MAX | 2 | mec | 1 |
| FUZZY_MAX | 3 | pipe | 0 |
| FUZZY_MAX | 4 | queue | 7 |
| PARAM_COMPARE | 0 | adev->gfx.mec.num_mec | > $2 |
| PARAM_COMPARE | 0 | adev->gfx.mec.num_pipe_per_mec | > $3 |
| PARAM_COMPARE | 0 | adev->gfx.mec.num_queue_per_pipe | > $4 |
| PARAM_COMPARE | 2 | mec | < $0->gfx.mec.num_mec |
| PARAM_COMPARE | 3 | pipe | < $0->gfx.mec.num_pipe_per_mec |
| PARAM_COMPARE | 4 | queue | < $0->gfx.mec.num_queue_per_pipe |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.bad_op_irq.num_types | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.eop_irq.num_types | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.mec.hpd_eop_obj->tbo.ttm->dma_ttm.sg->orig_nents | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.mec.mec_fw_obj->tbo.ttm->dma_ttm.sg->orig_nents | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.priv_inst_irq.num_types | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.priv_reg_irq.num_types | |
| UNITS | 2 | mec | unit_array_size |
| HALF_LOCKED2 | &pool->lock |
2424e8ec9bf51854 gfx_v12_0_sw_init() -> amdgpu_gfx_is_mec_queue_enabled()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 0 | adev->gfx.mec.num_pipe_per_mec | 1-u32max |
| PARAM_VALUE | 0 | adev->gfx.mec.num_queue_per_pipe | 1-u32max |
| PARAM_VALUE | 1 | xcc_id | 0 |
| PARAM_VALUE | 2 | mec | 0-s32max |
| PARAM_VALUE | 3 | pipe | 0-s32max |
| PARAM_VALUE | 4 | queue | 0-s32max |
| CAPPED_DATA | 2 | mec | 1 |
| CAPPED_DATA | 3 | pipe | 1 |
| CAPPED_DATA | 4 | queue | 1 |
| FUZZY_MAX | 2 | mec | 0 |
| FUZZY_MAX | 3 | pipe | 0 |
| FUZZY_MAX | 4 | queue | 0 |
| PARAM_COMPARE | 0 | adev->gfx.mec.num_mec | > $2 |
| PARAM_COMPARE | 0 | adev->gfx.mec.num_pipe_per_mec | > $3 |
| PARAM_COMPARE | 0 | adev->gfx.mec.num_queue_per_pipe | > $4 |
| PARAM_COMPARE | 2 | mec | < $0->gfx.mec.num_mec |
| PARAM_COMPARE | 3 | pipe | < $0->gfx.mec.num_pipe_per_mec |
| PARAM_COMPARE | 4 | queue | < $0->gfx.mec.num_queue_per_pipe |
| MEM_ZERO | 0 | adev->gfx.me.queue_bitmap | |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.bad_op_irq.num_types | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.eop_irq.num_types | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.mec.hpd_eop_obj->tbo.ttm->dma_ttm.sg->orig_nents | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.priv_inst_irq.num_types | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.priv_reg_irq.num_types | |
| UNITS | 2 | mec | unit_array_size |
| UNITS | 3 | pipe | unit_array_size |
| HALF_LOCKED2 | &pool->lock |
3d756af95eb3bd31 gfx_v12_1_sw_init() -> amdgpu_gfx_is_mec_queue_enabled()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 0 | adev->gfx.mec.num_pipe_per_mec | 1-u32max |
| PARAM_VALUE | 0 | adev->gfx.mec.num_queue_per_pipe | 1-u32max |
| PARAM_VALUE | 1 | xcc_id | 0-15 |
| PARAM_VALUE | 2 | mec | 0-s32max |
| PARAM_VALUE | 3 | pipe | 0-s32max |
| PARAM_VALUE | 4 | queue | 0-s32max |
| CAPPED_DATA | 1 | xcc_id | 1 |
| CAPPED_DATA | 2 | mec | 1 |
| CAPPED_DATA | 3 | pipe | 1 |
| CAPPED_DATA | 4 | queue | 1 |
| FUZZY_MAX | 2 | mec | 0 |
| FUZZY_MAX | 3 | pipe | 0 |
| FUZZY_MAX | 4 | queue | 0 |
| PARAM_COMPARE | 0 | adev->gfx.mec.num_mec | > $2 |
| PARAM_COMPARE | 0 | adev->gfx.mec.num_pipe_per_mec | > $3 |
| PARAM_COMPARE | 0 | adev->gfx.mec.num_queue_per_pipe | > $4 |
| PARAM_COMPARE | 2 | mec | < $0->gfx.mec.num_mec |
| PARAM_COMPARE | 3 | pipe | < $0->gfx.mec.num_pipe_per_mec |
| PARAM_COMPARE | 4 | queue | < $0->gfx.mec.num_queue_per_pipe |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.eop_irq.num_types | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.mec.hpd_eop_obj->tbo.ttm->dma_ttm.sg->orig_nents | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.priv_inst_irq.num_types | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.priv_reg_irq.num_types | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.rlc_poison_irq.num_types | |
| UNITS | 2 | mec | unit_array_size |
| HALF_LOCKED2 | &pool->lock |
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c gfx_v8_0_sw_init() -> amdgpu_gfx_is_mec_queue_enabled()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 0 | adev->gfx.mec.num_pipe_per_mec | 4 |
| PARAM_VALUE | 0 | adev->gfx.mec.num_queue_per_pipe | 8 |
| PARAM_VALUE | 1 | xcc_id | 0 |
| PARAM_VALUE | 2 | mec | 0-1 |
| PARAM_VALUE | 3 | pipe | 0-3 |
| PARAM_VALUE | 4 | queue | 0-7 |
| CAPPED_DATA | 0 | adev->gfx.num_gfx_rings | 1 |
| CAPPED_DATA | 2 | mec | 1 |
| FUZZY_MAX | 2 | mec | 1 |
| FUZZY_MAX | 3 | pipe | 3 |
| FUZZY_MAX | 4 | queue | 7 |
| PARAM_COMPARE | 0 | adev->gfx.mec.num_mec | > $2 |
| PARAM_COMPARE | 0 | adev->gfx.mec.num_pipe_per_mec | > $3 |
| PARAM_COMPARE | 0 | adev->gfx.mec.num_queue_per_pipe | > $4 |
| PARAM_COMPARE | 2 | mec | < $0->gfx.mec.num_mec |
| PARAM_COMPARE | 3 | pipe | < $0->gfx.mec.num_pipe_per_mec |
| PARAM_COMPARE | 4 | queue | < $0->gfx.mec.num_queue_per_pipe |
| HARD_MAX | 2 | mec | 1 |
| HARD_MAX | 3 | pipe | 3 |
| HARD_MAX | 4 | queue | 7 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.cp_ecc_error_irq.num_types | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.eop_irq.num_types | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.mec.hpd_eop_obj->tbo.ttm->dma_ttm.sg->orig_nents | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.priv_inst_irq.num_types | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.priv_reg_irq.num_types | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.sq_irq.num_types | |
| UNITS | 2 | mec | unit_array_size |
| HALF_LOCKED2 | &pool->lock |
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c gfx_v7_0_sw_init() -> amdgpu_gfx_is_mec_queue_enabled()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 0 | adev->gfx.mec.num_pipe_per_mec | 4 |
| PARAM_VALUE | 0 | adev->gfx.mec.num_queue_per_pipe | 8 |
| PARAM_VALUE | 1 | xcc_id | 0 |
| PARAM_VALUE | 2 | mec | 0-1 |
| PARAM_VALUE | 3 | pipe | 0-3 |
| PARAM_VALUE | 4 | queue | 0-7 |
| CAPPED_DATA | 0 | adev->gfx.num_gfx_rings | 1 |
| CAPPED_DATA | 2 | mec | 1 |
| FUZZY_MAX | 2 | mec | 1 |
| FUZZY_MAX | 3 | pipe | 3 |
| FUZZY_MAX | 4 | queue | 7 |
| PARAM_COMPARE | 0 | adev->gfx.mec.num_mec | > $2 |
| PARAM_COMPARE | 0 | adev->gfx.mec.num_pipe_per_mec | > $3 |
| PARAM_COMPARE | 0 | adev->gfx.mec.num_queue_per_pipe | > $4 |
| PARAM_COMPARE | 2 | mec | < $0->gfx.mec.num_mec |
| PARAM_COMPARE | 3 | pipe | < $0->gfx.mec.num_pipe_per_mec |
| PARAM_COMPARE | 4 | queue | < $0->gfx.mec.num_queue_per_pipe |
| HARD_MAX | 2 | mec | 1 |
| HARD_MAX | 3 | pipe | 3 |
| HARD_MAX | 4 | queue | 7 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.eop_irq.num_types | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.mec.hpd_eop_obj->tbo.ttm->dma_ttm.sg->orig_nents | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.priv_inst_irq.num_types | |
| NO_OVERFLOW_SIMPLE | 0 | adev->gfx.priv_reg_irq.num_types | |
| UNITS | 2 | mec | unit_array_size |
| HALF_LOCKED2 | &pool->lock |