Defined in 1 files as a prototype:
Defined in 1 files as a function:
Referenced in 10 files:
- drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c, line 827
- drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
- drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c, line 600
- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c, line 784
- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c, line 1262
- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c, line 842
- drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c, line 718
- drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c, line 924
- drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c, line 668
- drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c, line 705
Smatch caller information:
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c amdgpu_ring_commit() -> (struct amdgpu_ring_funcs)->end_use()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | ring | 4096-ptr_max |
| PARAM_VALUE | 0 | ring->adev->gfx.funcs->get_hdp_flush_mask | 0,1294107431044386816,7035510910386749440,8166760959833321472 |
| PARAM_VALUE | 0 | ring->adev->gfx.rlc.cs_data->section->reg_index | 0,4,40960,41022,41164,41174,41176,41179,41461,41471-41472,41530,41630,41632-41633,41635,41637-41638,41694,41701,41717,41920,62460,65472 |
| PARAM_VALUE | 0 | ring->adev->gfx.rlc.reg_funcs->rreg32 | 4096-ptr_max |
| PARAM_VALUE | 0 | ring->adev->mes.funcs->reset_hw_queue | 4096-ptr_max |
| PARAM_VALUE | 0 | ring->adev->nbio.hdp_flush_reg->ref_and_mask_cp8 | 256 |
| PARAM_VALUE | 0 | ring->adev->nbio.hdp_flush_reg->ref_and_mask_cp9 | 512 |
| PARAM_VALUE | 0 | ring->adev->nbio.hdp_flush_reg->ref_and_mask_sdma0 | 1024 |
| PARAM_VALUE | 0 | ring->adev->nbio.hdp_flush_reg->ref_and_mask_sdma1 | 2048 |
| PARAM_VALUE | 0 | ring->adev->reset_domain->sem.first_waiter->handoff_set | 0-1 |
| PARAM_VALUE | 0 | ring->adev->reset_domain->sem.first_waiter->type | 0-1 |
| PARAM_VALUE | 0 | ring->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | ring->funcs->end_use | 1-u64max |
| BUF_SIZE | 0 | ring | (-1),1360,2720,4080,13600,21760,87040 |
| BUF_SIZE | 0 | ring | (-1),1360,2720,4080,13600,21760,87040 |
| DATA_SOURCE | 0 | ring | $0 |
| CONTAINER | 0 | -184-8+0 | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HOST_DATA | 0 | ring->count_dw | 0-s32max[c] |
| HOST_DATA | 0 | ring->wptr | 0-u32max |
| HOST_DATA | 0 | ring->wptr_old | 0-u32max |
| HALF_LOCKED2 | &adev->reset_domain->sem | ||
| HALF_LOCKED2 | &adev->srbm_mutex | ||
| HALF_LOCKED2 | &kiq->ring_lock | ||
| HALF_LOCKED2 | &mux->lock | ||
| HALF_LOCKED2 | flags | ||
| HALF_LOCKED2 | global &drm_unplug_srcu | ||
| HALF_LOCKED2 | ring_lock |
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c amdgpu_ring_undo() -> (struct amdgpu_ring_funcs)->end_use()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | ring | 4096-ptr_max |
| PARAM_VALUE | 0 | ring->adev->gfx.funcs->get_hdp_flush_mask | 0,1294107431044386816,7035510910386749440,8166760959833321472 |
| PARAM_VALUE | 0 | ring->adev->gfx.rlc.cs_data->section->reg_index | 0,4,40960,41022,41164,41174,41176,41179,41461,41471-41472,41530,41630,41632-41633,41635,41637-41638,41694,41701,41717,41920,62460,65472 |
| PARAM_VALUE | 0 | ring->adev->nbio.hdp_flush_reg->ref_and_mask_cp8 | 256 |
| PARAM_VALUE | 0 | ring->adev->nbio.hdp_flush_reg->ref_and_mask_cp9 | 512 |
| PARAM_VALUE | 0 | ring->adev->nbio.hdp_flush_reg->ref_and_mask_sdma0 | 1024 |
| PARAM_VALUE | 0 | ring->adev->nbio.hdp_flush_reg->ref_and_mask_sdma1 | 2048 |
| PARAM_VALUE | 0 | ring->adev->reset_domain->sem.first_waiter->handoff_set | 0-1 |
| PARAM_VALUE | 0 | ring->adev->reset_domain->sem.first_waiter->type | 0-1 |
| PARAM_VALUE | 0 | ring->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | ring->funcs->end_use | 1-u64max |
| BUF_SIZE | 0 | ring | (-1),1360,21760 |
| BUF_SIZE | 0 | ring | (-1),1360,21760 |
| DATA_SOURCE | 0 | ring | $0 |
| CONTAINER | 0 | -184-8+0 | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| LOCK2 | flags | ||
| HALF_LOCKED2 | &adev->reset_domain->sem | ||
| HALF_LOCKED2 | &kiq->ring_lock | ||
| HALF_LOCKED2 | ring_lock |