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Defined in 1 files as a prototype:

Defined in 1 files as a function:

Referenced in 5 files:

Smatch caller information:

drivers/gpu/drm/amd/amdgpu/soc21.c soc21_get_register_value() -> amdgpu_read_indexed_register()

Type Parameter Key Value
PARAM_VALUE 0 adev 4096-ptr_max
PARAM_VALUE 0 adev->asic_funcs 4096-ptr_max
PARAM_VALUE 0 adev->gfx.gfx_off_mutex.first_waiter 0,4096-ptr_max
PARAM_VALUE 0 adev->gfx.gfx_off_mutex.osq.tail.counter 0-s32max
PARAM_VALUE 0 adev->reg_offset 4096-ptr_max
PARAM_VALUE 0 adev->reset_domain 4096-ptr_max
PARAM_VALUE 1 se_num 0-3,u32max
PARAM_VALUE 2 sh_num 0-1,u32max
CAPPED_DATA 3 reg_offset 1
DATA_SOURCE 0 adev $0
DATA_SOURCE 1 se_num $2
DATA_SOURCE 2 sh_num $3
DATA_SOURCE 3 reg_offset $4
USER_DATA 1 se_num 0-3[c]
USER_DATA 2 sh_num 0-1[c]
LOCK2 &adev->reset_domain->sem
TYPE_LOCK (struct amdgpu_reset_domain)->sem

drivers/gpu/drm/amd/amdgpu/nv.c nv_get_register_value() -> amdgpu_read_indexed_register()

Type Parameter Key Value
PARAM_VALUE 0 adev 4096-ptr_max
PARAM_VALUE 0 adev->asic_funcs 4096-ptr_max
PARAM_VALUE 0 adev->gfx.gfx_off_mutex.first_waiter 0,4096-ptr_max
PARAM_VALUE 0 adev->gfx.gfx_off_mutex.osq.tail.counter 0-s32max
PARAM_VALUE 0 adev->reg_offset 4096-ptr_max
PARAM_VALUE 0 adev->reset_domain 4096-ptr_max
PARAM_VALUE 1 se_num 0-3,u32max
PARAM_VALUE 2 sh_num 0-1,u32max
CAPPED_DATA 3 reg_offset 1
DATA_SOURCE 0 adev $0
DATA_SOURCE 1 se_num $2
DATA_SOURCE 2 sh_num $3
DATA_SOURCE 3 reg_offset $4
USER_DATA 1 se_num 0-3[c]
USER_DATA 2 sh_num 0-1[c]
LOCK2 &adev->reset_domain->sem
TYPE_LOCK (struct amdgpu_reset_domain)->sem

drivers/gpu/drm/amd/amdgpu/soc15.c soc15_get_register_value() -> amdgpu_read_indexed_register()

Type Parameter Key Value
PARAM_VALUE 0 adev 4096-ptr_max
PARAM_VALUE 0 adev->asic_funcs 4096-ptr_max
PARAM_VALUE 0 adev->gfx.gfx_off_mutex.first_waiter 0,4096-ptr_max
PARAM_VALUE 0 adev->gfx.gfx_off_mutex.osq.tail.counter 0-s32max
PARAM_VALUE 0 adev->reg_offset 4096-ptr_max
PARAM_VALUE 0 adev->reset_domain 4096-ptr_max
PARAM_VALUE 1 se_num 0-3,u32max
PARAM_VALUE 2 sh_num 0-1,u32max
CAPPED_DATA 3 reg_offset 1
DATA_SOURCE 0 adev $0
DATA_SOURCE 1 se_num $2
DATA_SOURCE 2 sh_num $3
DATA_SOURCE 3 reg_offset $4
USER_DATA 1 se_num 0-3[c]
USER_DATA 2 sh_num 0-1[c]
LOCK2 &adev->reset_domain->sem
TYPE_LOCK (struct amdgpu_reset_domain)->sem

drivers/gpu/drm/amd/amdgpu/soc_v1_0.c soc_v1_0_get_register_value() -> amdgpu_read_indexed_register()

Type Parameter Key Value
PARAM_VALUE 0 adev 4096-ptr_max
PARAM_VALUE 0 adev->asic_funcs 4096-ptr_max
PARAM_VALUE 0 adev->gfx.gfx_off_mutex.first_waiter 0,4096-ptr_max
PARAM_VALUE 0 adev->gfx.gfx_off_mutex.osq.tail.counter 0-s32max
PARAM_VALUE 0 adev->reg_offset 4096-ptr_max
PARAM_VALUE 0 adev->reset_domain 4096-ptr_max
PARAM_VALUE 1 se_num 0-3,u32max
PARAM_VALUE 2 sh_num 0-1,u32max
CAPPED_DATA 3 reg_offset 1
DATA_SOURCE 0 adev $0
DATA_SOURCE 1 se_num $2
DATA_SOURCE 2 sh_num $3
DATA_SOURCE 3 reg_offset $4
USER_DATA 1 se_num 0-3[c]
USER_DATA 2 sh_num 0-1[c]
LOCK2 &adev->reset_domain->sem
TYPE_LOCK (struct amdgpu_reset_domain)->sem

drivers/gpu/drm/amd/amdgpu/soc24.c soc24_get_register_value() -> amdgpu_read_indexed_register()

Type Parameter Key Value
PARAM_VALUE 0 adev 4096-ptr_max
PARAM_VALUE 0 adev->asic_funcs 4096-ptr_max
PARAM_VALUE 0 adev->gfx.gfx_off_mutex.first_waiter 0,4096-ptr_max
PARAM_VALUE 0 adev->gfx.gfx_off_mutex.osq.tail.counter 0-s32max
PARAM_VALUE 0 adev->reg_offset 4096-ptr_max
PARAM_VALUE 0 adev->reset_domain 4096-ptr_max
PARAM_VALUE 1 se_num 0-3,u32max
PARAM_VALUE 2 sh_num 0-1,u32max
CAPPED_DATA 3 reg_offset 1
DATA_SOURCE 0 adev $0
DATA_SOURCE 1 se_num $2
DATA_SOURCE 2 sh_num $3
DATA_SOURCE 3 reg_offset $4
USER_DATA 1 se_num 0-3[c]
USER_DATA 2 sh_num 0-1[c]
LOCK2 &adev->reset_domain->sem
TYPE_LOCK (struct amdgpu_reset_domain)->sem