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Defined in 1 files as a prototype:

Defined in 1 files as a function:

Referenced in 2 files:

Smatch caller information:

drivers/gpu/drm/i915/display/intel_pps.c vlv_power_sequencer_kick() -> chv_phy_powergate_ch()

Type Parameter Key Value
PARAM_VALUE 0 display 4096-ptr_max
PARAM_VALUE 0 display->drm 0,4096-ptr_max
PARAM_VALUE 0 display->info.__device_info 4096-ptr_max
PARAM_VALUE 0 display->params.enable_dmc_wl 0-1
PARAM_VALUE 0 display->platform.cherryview 1
PARAM_VALUE 0 display->wl.taken 1
PARAM_VALUE 0 display->wl.work.timer.entry->pprev 4096-ptr_max
PARAM_VALUE 1 phy 0-1
PARAM_VALUE 2 ch 0-1
PARAM_VALUE 3 override 1
DATA_SOURCE 1 phy r vlv_pipe_to_phy
DATA_SOURCE 2 ch r vlv_pipe_to_channel
RX_PATH
TASK_NOT_RUNNING
HALF_LOCKED2 &display->pps.mutex

drivers/gpu/drm/i915/display/intel_pps.c vlv_power_sequencer_kick() -> chv_phy_powergate_ch()

Type Parameter Key Value
PARAM_VALUE 0 display 4096-ptr_max
PARAM_VALUE 0 display->drm 0,4096-ptr_max
PARAM_VALUE 0 display->info.__device_info 4096-ptr_max
PARAM_VALUE 0 display->params.enable_dmc_wl 0-1
PARAM_VALUE 0 display->parent 4096-ptr_max
PARAM_VALUE 0 display->platform.cherryview 1
PARAM_VALUE 0 display->power.domains.async_put_work.work.entry.next 1-u64max
PARAM_VALUE 0 display->power.domains.async_put_work.work.entry.next->next 1-u64max
PARAM_VALUE 0 display->power.domains.async_put_work.work.entry.next->prev 4096-ptr_max
PARAM_VALUE 0 display->power.domains.async_put_work.work.entry.prev 1-u64max
PARAM_VALUE 0 display->power.domains.async_put_work.work.entry.prev->next 1-u64max
PARAM_VALUE 0 display->power.domains.async_put_work.work.entry.prev->prev 1-u64max
PARAM_VALUE 0 display->power.domains.lock.dep_map->name 0-255
PARAM_VALUE 0 display->power.domains.lock.first_waiter->list.prev->next 5159360019465732096
PARAM_VALUE 0 display->power.domains.lock.first_waiter->list.prev->prev 5159360019465732096
PARAM_VALUE 0 display->power.domains.lock.first_waiter->task->blocked_lock.dep_map->name 0-255
PARAM_VALUE 0 display->power.domains.lock.first_waiter->task->blocked_lock.owner (-1)
PARAM_VALUE 0 display->power.domains.lock.first_waiter->task->blocked_lock.owner_cpu 4294967295
PARAM_VALUE 0 display->power.domains.lock.first_waiter->task->blocked_lock.raw_lock.val.counter s32min-s32max
PARAM_VALUE 0 display->power.domains.lock.first_waiter->task->usage.refs.counter s32min-s32max
PARAM_VALUE 0 display->power.domains.lock.osq.tail.counter 0-s32max
PARAM_VALUE 0 display->wl.taken 1
PARAM_VALUE 0 display->wl.work.timer.entry->pprev 4096-ptr_max
PARAM_VALUE 0 display->wl.work.work.entry.next->next 1-u64max
PARAM_VALUE 0 display->wl.work.work.entry.next->prev 4096-ptr_max
PARAM_VALUE 0 display->wl.work.work.entry.prev->next 1-u64max
PARAM_VALUE 0 display->wl.work.work.entry.prev->prev 1-u64max
PARAM_VALUE 0 *display->irq.pipestat_irq_mask 0-4294967295
PARAM_VALUE 0 *display->power.chv_phy_assert 0-1
PARAM_VALUE 1 phy 0-1
PARAM_VALUE 2 ch 0-1
PARAM_VALUE 3 override 0
DATA_SOURCE 1 phy r vlv_pipe_to_phy
DATA_SOURCE 2 ch r vlv_pipe_to_channel
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HOST_DATA 0 display->dmc.dmc->dc6_allowed.dc5_start 0-4294967295
HOST_DATA 0 display->power.domains.dc_state 0-u32max
HALF_LOCKED2 &display->pps.mutex

drivers/gpu/drm/i915/display/intel_dpio_phy.c chv_phy_pre_pll_enable() -> chv_phy_powergate_ch()

Type Parameter Key Value
PARAM_VALUE 1 phy 0
PARAM_VALUE 2 ch 1
PARAM_VALUE 3 override 1
RX_PATH
TASK_NOT_RUNNING

drivers/gpu/drm/i915/display/intel_dpio_phy.c chv_phy_release_cl2_override() -> chv_phy_powergate_ch()

Type Parameter Key Value
PARAM_VALUE 1 phy 0
PARAM_VALUE 2 ch 1
PARAM_VALUE 3 override 0
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL