Open Menu /

Defined in 1 files as a function:

Referenced in 1 files:

Smatch caller information:

drivers/gpu/drm/radeon/ci_dpm.c ci_update_vce_dpm() -> ci_enable_vce_dpm()

Type Parameter Key Value
PARAM_VALUE 0 rdev 4096-ptr_max
PARAM_VALUE 0 rdev->asic 4096-ptr_max
PARAM_VALUE 0 rdev->mman.bdev.dev_mapping->host->i_sb->s_export_op->encode_fh 0,2,1398972869330624512,1616549510479982592,2037984473558433792
PARAM_VALUE 0 rdev->mman.bdev.dev_mapping->host->i_sb->s_export_op->fh_to_dentry 0,8684,447817974243774464,687732489194512384,742201802719268864
PARAM_VALUE 0 rdev->mman.bdev.dev_mapping->host->i_sb->s_export_op->fh_to_parent 0,5297,148606482432692224,436469935444291584,467281172929331200
PARAM_VALUE 0 rdev->mman.bdev.dev_mapping->host->i_sb->s_export_op->get_parent 0,8931,264940071972966400,291591359766798336,565128213429456896
PARAM_VALUE 0 rdev->mmio_idx_lock.rlock.dep_map->name 0-255
PARAM_VALUE 0 rdev->pciep_idx_lock.rlock.dep_map->name 0-255
PARAM_VALUE 0 rdev->pm.dpm.high_pixelclock_count 0-s32max
PARAM_VALUE 0 rdev->pm.dpm.new_active_crtc_count 0-s32max
PARAM_VALUE 0 rdev->pm.dpm.priv 4096-ptr_max
PARAM_VALUE 0 rdev->pm.dpm.priv->dpm_level_enable_mask.mclk_dpm_enable_mask 0-1
PARAM_VALUE 0 rdev->pm.dpm.priv->dpm_level_enable_mask.pcie_dpm_enable_mask 0-1
PARAM_VALUE 0 rdev->pm.dpm.priv->dpm_level_enable_mask.sclk_dpm_enable_mask 0-1
PARAM_VALUE 0 rdev->pm.dpm.priv->last_mclk_dpm_enable_mask 0-1
PARAM_VALUE 0 rdev->pm.dpm.priv->need_update_smu7_dpm_table 0-3,8-11
PARAM_VALUE 0 rdev->pm.dpm.requested_ps 1-u64max
PARAM_VALUE 0 rdev->pm.dpm_enabled 1
PARAM_VALUE 0 rdev->pm.mclk_lock.osq.tail.counter 0-s32max
PARAM_VALUE 0 rdev->pm.mclk_lock.wait_lock.owner (-1)
PARAM_VALUE 0 rdev->pm.mclk_lock.wait_lock.owner_cpu u32max
PARAM_VALUE 0 rdev->pm.mclk_lock.wait_lock.raw_lock.val.counter 0-s32max
PARAM_VALUE 0 rdev->pm.mutex.first_waiter 0,4096-ptr_max
PARAM_VALUE 0 rdev->pm.mutex.osq.tail.counter 0-s32max
PARAM_VALUE 0 rdev->pm.mutex.wait_lock.owner (-1)
PARAM_VALUE 0 rdev->pm.mutex.wait_lock.owner_cpu u32max
PARAM_VALUE 0 rdev->pm.mutex.wait_lock.raw_lock.val.counter 0-s32max
PARAM_VALUE 0 rdev->pm.pm_method 2
PARAM_VALUE 0 rdev->ring_lock.first_waiter 0,4096-ptr_max
PARAM_VALUE 0 rdev->ring_lock.osq.tail.counter 0-s32max
PARAM_VALUE 0 rdev->ring_lock.wait_lock.owner (-1)
PARAM_VALUE 0 rdev->ring_lock.wait_lock.owner_cpu u32max
PARAM_VALUE 0 rdev->smc_idx_lock.rlock.dep_map->name 0-255
PARAM_VALUE 0 rdev->uvd_idx_lock.rlock.dep_map->name 0-255
PARAM_VALUE 0 rdev->vce.vcpu_bo->tbo.bdev->dev_mapping->host->i_sb->s_export_op->fh_to_parent 0,5297,148606482432692224,436469935444291584,467281172929331200
PARAM_VALUE 1 enable 1
BUF_SIZE 0 rdev s32min-(-1),1-s32max
BUF_SIZE 0 rdev s32min-(-1),1-s32max
CAPPED_DATA 0 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count 1
CAPPED_DATA 0 rdev->pm.dpm.new_active_crtc_count 1
CAPPED_DATA 0 rdev->pm.dpm.num_ps 1
CAPPED_DATA 0 rdev->pm.dpm.priv->dpm_table.mclk_table.count 1
CAPPED_DATA 0 rdev->pm.dpm.priv->dpm_table.pcie_speed_table.count 1
CAPPED_DATA 0 rdev->pm.dpm.priv->dpm_table.sclk_table.count 1
CAPPED_DATA 0 rdev->pm.dpm.requested_ps 1
DATA_SOURCE 0 rdev $0
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 rdev->config.cik.tile_config 0-16383[c]
HOST_DATA 0 rdev->config.r100.hdp_cntl 0-u32max
HOST_DATA 0 rdev->config.r300.hdp_cntl 0-u32max
HOST_DATA 0 rdev->config.r600.backend_map 0-3[c]
HOST_DATA 0 rdev->config.r600.tile_config 0-262143[c]
HOST_DATA 0 rdev->config.rv770.tile_config 0,2048-u32max[c]
HOST_DATA 0 rdev->gart.num_cpu_pages 0-524287[c]
HOST_DATA 0 rdev->irq.stat_regs.cik.d1grph_int 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.cik.d2grph_int 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.cik.d3grph_int 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.cik.d4grph_int 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.cik.d5grph_int 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.cik.d6grph_int 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.cik.disp_int 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.cik.disp_int_cont 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.cik.disp_int_cont2 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.cik.disp_int_cont3 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.cik.disp_int_cont4 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.cik.disp_int_cont5 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.cik.disp_int_cont6 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.r500.disp_int 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.r500.hdmi0_status 0,268435456
HOST_DATA 0 rdev->mc.aper_base 0-1099511627775
HOST_DATA 0 rdev->mc.gtt_size 0-s32max[c]
HOST_DATA 0 rdev->mc.gtt_start 0-u64max[c]
HOST_DATA 0 rdev->mc.mc_vram_size 0-4503599626321920
HOST_DATA 0 rdev->mc.real_vram_size 0-4503599626321920
HOST_DATA 0 rdev->mc.vram_end 0-9223372039002259453,u64max[c]
HOST_DATA 0 rdev->mc.vram_start 0-9223372036854775807[c]
HOST_DATA 0 rdev->num_gb_pipes 2-4[c]
LOCK2 &rdev->pm.mclk_lock
LOCK2 &rdev->pm.mutex
LOCK2 &rdev->ring_lock
HALF_LOCKED2 &of->mutex
HALF_LOCKED2 &pool->lock
HALF_LOCKED2 &rdev->exclusive_lock
TYPE_LOCK (struct radeon_device)->ring_lock
TYPE_LOCK (struct radeon_pm)->mclk_lock
TYPE_LOCK (struct radeon_pm)->mutex

drivers/gpu/drm/radeon/ci_dpm.c ci_update_vce_dpm() -> ci_enable_vce_dpm()

Type Parameter Key Value
PARAM_VALUE 0 rdev 4096-ptr_max
PARAM_VALUE 0 rdev->asic 4096-ptr_max
PARAM_VALUE 0 rdev->asic->get_xclk 0,4096-ptr_max
PARAM_VALUE 0 rdev->gart.robj->tbo.bdev->dev_mapping->host->i_sb->s_export_op->encode_fh 0,2,1398972869330624512,1616549510479982592,2037984473558433792
PARAM_VALUE 0 rdev->gart.robj->tbo.bdev->dev_mapping->host->i_sb->s_export_op->fh_to_dentry 0,8684,447817974243774464,687732489194512384,742201802719268864
PARAM_VALUE 0 rdev->gart.robj->tbo.bdev->dev_mapping->host->i_sb->s_export_op->fh_to_parent 0,5297,148606482432692224,436469935444291584,467281172929331200
PARAM_VALUE 0 rdev->gart.robj->tbo.bdev->dev_mapping->host->i_sb->s_export_op->get_parent 0,8931,264940071972966400,291591359766798336,565128213429456896
PARAM_VALUE 0 rdev->pciep_idx_lock.rlock.dep_map->name 0-255
PARAM_VALUE 0 rdev->pm.dpm.high_pixelclock_count 0-s32max
PARAM_VALUE 0 rdev->pm.dpm.new_active_crtc_count 0-s32max
PARAM_VALUE 0 rdev->pm.dpm.priv 4096-ptr_max
PARAM_VALUE 0 rdev->pm.dpm.priv->dpm_level_enable_mask.mclk_dpm_enable_mask 0-1
PARAM_VALUE 0 rdev->pm.dpm.priv->dpm_level_enable_mask.pcie_dpm_enable_mask 0-1
PARAM_VALUE 0 rdev->pm.dpm.priv->dpm_level_enable_mask.sclk_dpm_enable_mask 0-1
PARAM_VALUE 0 rdev->pm.dpm.priv->last_mclk_dpm_enable_mask 0-1
PARAM_VALUE 0 rdev->pm.dpm.priv->need_update_smu7_dpm_table 0-3,8-11
PARAM_VALUE 0 rdev->pm.dpm.requested_ps 1-u64max
PARAM_VALUE 0 rdev->pm.dpm_enabled 1
PARAM_VALUE 0 rdev->pm.mclk_lock.osq.tail.counter 0-s32max
PARAM_VALUE 0 rdev->pm.mclk_lock.wait_lock.owner (-1)
PARAM_VALUE 0 rdev->pm.mclk_lock.wait_lock.owner_cpu u32max
PARAM_VALUE 0 rdev->pm.mclk_lock.wait_lock.raw_lock.val.counter 0-s32max
PARAM_VALUE 0 rdev->pm.mutex.first_waiter 0,4096-ptr_max
PARAM_VALUE 0 rdev->pm.mutex.osq.tail.counter 0-s32max
PARAM_VALUE 0 rdev->pm.mutex.wait_lock.owner (-1)
PARAM_VALUE 0 rdev->pm.mutex.wait_lock.owner_cpu u32max
PARAM_VALUE 0 rdev->pm.mutex.wait_lock.raw_lock.val.counter 0-s32max
PARAM_VALUE 0 rdev->pm.pm_method 2
PARAM_VALUE 0 rdev->ring_lock.first_waiter 0,4096-ptr_max
PARAM_VALUE 0 rdev->ring_lock.osq.tail.counter 0-s32max
PARAM_VALUE 0 rdev->ring_lock.wait_lock.owner (-1)
PARAM_VALUE 0 rdev->ring_lock.wait_lock.owner_cpu u32max
PARAM_VALUE 0 rdev->uvd_idx_lock.rlock.dep_map->name 0-255
PARAM_VALUE 0 rdev->vce.vcpu_bo->tbo.bdev->dev_mapping->host->i_sb->s_export_op->fh_to_parent 0,4672,148606482432692224,436469935444291584,457356038048772096
PARAM_VALUE 1 enable 0
BUF_SIZE 0 rdev s32min-(-1),1-s32max
BUF_SIZE 0 rdev s32min-(-1),1-s32max
CAPPED_DATA 0 rdev->pm.dpm.new_active_crtc_count 1
CAPPED_DATA 0 rdev->pm.dpm.num_ps 1
CAPPED_DATA 0 rdev->pm.dpm.priv->dpm_table.mclk_table.count 1
CAPPED_DATA 0 rdev->pm.dpm.priv->dpm_table.pcie_speed_table.count 1
CAPPED_DATA 0 rdev->pm.dpm.priv->dpm_table.sclk_table.count 1
CAPPED_DATA 0 rdev->pm.dpm.requested_ps 1
DATA_SOURCE 0 rdev $0
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 rdev->config.cik.tile_config 0-16383[c]
HOST_DATA 0 rdev->config.r100.hdp_cntl 0-u32max
HOST_DATA 0 rdev->config.r300.hdp_cntl 0-u32max
HOST_DATA 0 rdev->config.r600.backend_map 0-3[c]
HOST_DATA 0 rdev->config.r600.tile_config 0-262143[c]
HOST_DATA 0 rdev->config.rv770.tile_config 0,2048-u32max[c]
HOST_DATA 0 rdev->gart.num_cpu_pages 0-524287[c]
HOST_DATA 0 rdev->irq.stat_regs.cik.d1grph_int 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.cik.d2grph_int 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.cik.d3grph_int 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.cik.d4grph_int 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.cik.d5grph_int 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.cik.d6grph_int 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.cik.disp_int 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.cik.disp_int_cont 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.cik.disp_int_cont2 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.cik.disp_int_cont3 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.cik.disp_int_cont4 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.cik.disp_int_cont5 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.cik.disp_int_cont6 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.r500.disp_int 0-u32max
HOST_DATA 0 rdev->irq.stat_regs.r500.hdmi0_status 0,268435456
HOST_DATA 0 rdev->mc.aper_base 0-1099511627775
HOST_DATA 0 rdev->mc.gtt_size 0-s32max[c]
HOST_DATA 0 rdev->mc.gtt_start 0-u64max[c]
HOST_DATA 0 rdev->mc.mc_vram_size 0-4503599626321920
HOST_DATA 0 rdev->mc.real_vram_size 0-4503599626321920
HOST_DATA 0 rdev->mc.vram_end 0-9223372039002259453,u64max[c]
HOST_DATA 0 rdev->mc.vram_start 0-9223372036854775807[c]
HOST_DATA 0 rdev->num_gb_pipes 2-4[c]
LOCK2 &rdev->pm.mclk_lock
LOCK2 &rdev->pm.mutex
LOCK2 &rdev->ring_lock
HALF_LOCKED2 &of->mutex
HALF_LOCKED2 &pool->lock
HALF_LOCKED2 &rdev->exclusive_lock
TYPE_LOCK (struct radeon_device)->ring_lock
TYPE_LOCK (struct radeon_pm)->mclk_lock
TYPE_LOCK (struct radeon_pm)->mutex