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Defined in 1 files as a function:

Referenced in 1 files:

Smatch caller information:

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c __release_guc_id() -> context_guc_id_invalid()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
DATA_SOURCE 0 ce $1
PREEMPT_ADD
RX_PATH
TASK_NOT_RUNNING
LOCK2 &guc->submission_state.lock
HALF_LOCKED2 flags
TYPE_LOCK (struct intel_guc)->submission_state.lock

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c bypass_sched_disable() -> context_guc_id_invalid()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce->timeline (-1),728
BUF_SIZE 0 ce->vm (-1)-0,1208
DATA_SOURCE 0 ce $1
STR_LEN 0 ce->engine (-1),3,6
STR_LEN 0 ce->gem_context->i915 (-1),1,4
PREEMPT_ADD
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 ce->engine->execlists.reset_ccid 0-u32max
HOST_DATA 0 ce->engine->gt->i915->uncore.fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->gt->uc.guc.mmio_msg 0
HOST_DATA 0 ce->engine->gt->uc.guc.timestamp.gt_stamp 0-u64max
HOST_DATA 0 ce->engine->gt->uncore->fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->uncore->fifo_count 0-127,u32max
NO_OVERFLOW_SIMPLE 0 ce->ring->effective_size
NO_OVERFLOW_SIMPLE 0 ce->ring->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->fence_size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->vm->total
NO_OVERFLOW_SIMPLE 0 ce->ring_size
NO_OVERFLOW_SIMPLE 0 ce->state->fence_size
NO_OVERFLOW_SIMPLE 0 ce->state->size
LOCK2 flags
LOCK2 0 &ce->guc_state.lock
HALF_LOCKED2 0 &ce->pin_mutex
HALF_LOCKED2 0 &ce->timeline->mutex
TYPE_LOCK (struct intel_context)->guc_state.lock

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c context_cant_unblock() -> context_guc_id_invalid()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce (-1)-s32max
DATA_SOURCE 0 ce $0
BIT_INFO 0 ce->guc_state.sched_state 0x0,0xffe003f3
PREEMPT_ADD
LOCK2 flags
LOCK2 0 &ce->guc_state.lock
HALF_LOCKED2 &pool->lock
TYPE_LOCK (struct intel_context)->guc_state.lock

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c guc_context_destroy() -> context_guc_id_invalid()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
PREEMPT_ADD <- disables preempt
LOCK2 &guc->submission_state.lock
LOCK2 flags
TYPE_LOCK (struct intel_guc)->submission_state.lock

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c guc_context_revoke() -> context_guc_id_invalid()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
DATA_SOURCE 0 ce $0
PREEMPT_ADD <- disables preempt
RX_PATH
TASK_NOT_RUNNING
LOCK2 flags
LOCK2 0 &ce->guc_state.lock
HALF_LOCKED2 &ctx->engines_mutex
TYPE_LOCK (struct intel_context)->guc_state.lock

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c guc_kernel_context_pin() -> context_guc_id_invalid()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
DATA_SOURCE 0 ce $1
RX_PATH
TASK_NOT_RUNNING
LOCK2 __flags
HALF_LOCKED2 &gt->reset.mutex

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c pin_guc_id() -> context_guc_id_invalid()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce->timeline (-1),728
BUF_SIZE 0 ce->vm (-1),1208
DATA_SOURCE 0 ce $1
STR_LEN 0 ce->engine (-1),3,6-7,11,14,17
PREEMPT_ADD <- disables preempt
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 ce->engine->execlists.reset_ccid 0-u32max
HOST_DATA 0 ce->engine->gt->i915->uncore.fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->gt->uc.guc.mmio_msg 0
HOST_DATA 0 ce->engine->gt->uc.guc.timestamp.gt_stamp 0-u64max
HOST_DATA 0 ce->engine->gt->uncore->fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->uncore->fifo_count 0-127,u32max
NO_OVERFLOW_SIMPLE 0 ce->ring->effective_size
NO_OVERFLOW_SIMPLE 0 ce->ring->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->fence_size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->vm->total
NO_OVERFLOW_SIMPLE 0 ce->ring_size
NO_OVERFLOW_SIMPLE 0 ce->state->fence_size
NO_OVERFLOW_SIMPLE 0 ce->state->size
LOCK2 &guc->submission_state.lock
LOCK2 flags
HALF_LOCKED2 __flags
HALF_LOCKED2 0 ce->ring->vma->obj->base.resv
HALF_LOCKED2 0 ce->state->obj->base.resv
HALF_LOCKED2 0 ce->timeline->hwsp_ggtt->obj->base.resv
HALF_LOCKED2 0 &ce->pin_mutex
TYPE_LOCK (struct intel_guc)->submission_state.lock

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c unpin_guc_id() -> context_guc_id_invalid()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce->timeline (-1),728
BUF_SIZE 0 ce->vm (-1)-0,1208
CAPPED_DATA 0 ce 1
DATA_SOURCE 0 ce $1
STR_LEN 0 ce->engine (-1),3,6
STR_LEN 0 ce->gem_context->i915 (-1),1,4
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 ce->engine->execlists.reset_ccid 0-u32max
HOST_DATA 0 ce->engine->gt->i915->uncore.fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->gt->uc.guc.mmio_msg 0
HOST_DATA 0 ce->engine->gt->uc.guc.timestamp.gt_stamp 0-u64max
HOST_DATA 0 ce->engine->gt->uncore->fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->uncore->fifo_count 0-127,u32max
NO_OVERFLOW_SIMPLE 0 ce->ring->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->fence_size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->obj->base.size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->vm->total
NO_OVERFLOW_SIMPLE 0 ce->ring_size
NO_OVERFLOW_SIMPLE 0 ce->state->fence_size
NO_OVERFLOW_SIMPLE 0 ce->state->size
HALF_LOCKED2 __flags
HALF_LOCKED2 0 &ce->pin_mutex
HALF_LOCKED2 0 &ce->timeline->mutex

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c unpin_guc_id() -> context_guc_id_invalid()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
PARAM_VALUE 0 ce->guc_id.id 0-65534
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce->timeline (-1),728
BUF_SIZE 0 ce->vm (-1)-0,1208
CAPPED_DATA 0 ce 1
DATA_SOURCE 0 ce $1
STR_LEN 0 ce->engine (-1),3,6
STR_LEN 0 ce->gem_context->i915 (-1),1,4
PREEMPT_ADD <- disables preempt
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 ce->engine->execlists.reset_ccid 0-u32max
HOST_DATA 0 ce->engine->gt->i915->uncore.fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->gt->uc.guc.mmio_msg 0
HOST_DATA 0 ce->engine->gt->uc.guc.timestamp.gt_stamp 0-u64max
HOST_DATA 0 ce->engine->gt->uncore->fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->uncore->fifo_count 0-127,u32max
NO_OVERFLOW_SIMPLE 0 ce->ring->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->fence_size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->obj->base.size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->vm->total
NO_OVERFLOW_SIMPLE 0 ce->ring_size
NO_OVERFLOW_SIMPLE 0 ce->state->fence_size
NO_OVERFLOW_SIMPLE 0 ce->state->size
LOCK2 &guc->submission_state.lock
LOCK2 flags
HALF_LOCKED2 __flags
HALF_LOCKED2 0 &ce->pin_mutex
HALF_LOCKED2 0 &ce->timeline->mutex
TYPE_LOCK (struct intel_guc)->submission_state.lock