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Defined in 1 files as a function:

Referenced in 2 files:

Smatch caller information:

drivers/gpu/drm/i915/gt/intel_lrc.c check_ring_start() -> context_wa_bb_offset()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
CAPPED_DATA 0 ce 1
DATA_SOURCE 0 ce $0

drivers/gpu/drm/i915/gt/intel_lrc.c context_wabb() -> context_wa_bb_offset()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce->timeline (-1),728
BUF_SIZE 0 ce->vm (-1),1208
DATA_SOURCE 0 ce $0
STR_LEN 0 ce (-1),3-4,6-8,11,14,17,19,21,23
STR_LEN 0 ce (-1),3-4,6-8,11,14,17,19,21,23
STR_LEN 0 ce->engine (-1),3,6-7,11,14,17
PREEMPT_ADD
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 ce->engine->execlists.reset_ccid 0-u32max
HOST_DATA 0 ce->engine->gt->i915->uncore.fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->gt->uc.guc.mmio_msg 0
HOST_DATA 0 ce->engine->gt->uncore->fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->uncore->fifo_count 0-127,u32max
NO_OVERFLOW_SIMPLE 0 ce->ring->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->fence_size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->obj->base.size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->vm->total
NO_OVERFLOW_SIMPLE 0 ce->ring_size
NO_OVERFLOW_SIMPLE 0 ce->state->fence_size
NO_OVERFLOW_SIMPLE 0 ce->state->size
HALF_LOCKED2 0 ce->ring->vma->obj->base.resv
HALF_LOCKED2 0 ce->state->obj->base.resv
HALF_LOCKED2 0 ce->timeline->hwsp_ggtt->obj->base.resv
HALF_LOCKED2 0 &ce->pin_mutex

drivers/gpu/drm/i915/gt/intel_lrc.c emit_wabb_ctx_canary() -> context_wa_bb_offset()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce->timeline (-1),728
BUF_SIZE 0 ce->vm (-1),1208
DATA_SOURCE 0 ce $0
STR_LEN 0 ce (-1),3-4,6-8,11,14,17,19,21,23
STR_LEN 0 ce (-1),3-4,6-8,11,14,17,19,21,23
STR_LEN 0 ce->engine (-1),3,6-7,11,14,17
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 ce->engine->execlists.reset_ccid 0-u32max
HOST_DATA 0 ce->engine->gt->i915->uncore.fifo_count 0-126,u32max
HOST_DATA 0 ce->engine->gt->uc.guc.mmio_msg 0
HOST_DATA 0 ce->engine->gt->uncore->fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->uncore->fifo_count 0-127,u32max
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->fence_size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->obj->base.size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->vm->total
NO_OVERFLOW_SIMPLE 0 ce->ring_size
NO_OVERFLOW_SIMPLE 0 ce->state->fence_size
NO_OVERFLOW_SIMPLE 0 ce->state->size
HALF_LOCKED2 0 ce->ring->vma->obj->base.resv
HALF_LOCKED2 0 ce->state->obj->base.resv
HALF_LOCKED2 0 ce->timeline->hwsp_ggtt->obj->base.resv
HALF_LOCKED2 0 &ce->pin_mutex

drivers/gpu/drm/i915/gt/intel_lrc.c lrc_indirect_bb() -> context_wa_bb_offset()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce->timeline (-1),728
BUF_SIZE 0 ce->vm (-1),1208
DATA_SOURCE 0 ce $0
STR_LEN 0 ce (-1),3-4,6-8,11,14,17,19,21,23
STR_LEN 0 ce (-1),3-4,6-8,11,14,17,19,21,23
STR_LEN 0 ce->engine (-1),3,6-7,11,14,17
PREEMPT_ADD
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 ce->engine->execlists.reset_ccid 0-u32max
HOST_DATA 0 ce->engine->gt->i915->uncore.fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->gt->uc.guc.mmio_msg 0
HOST_DATA 0 ce->engine->gt->uncore->fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->uncore->fifo_count 0-127,u32max
NO_OVERFLOW_SIMPLE 0 ce->ring->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->fence_size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->obj->base.size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->vm->total
NO_OVERFLOW_SIMPLE 0 ce->ring_size
NO_OVERFLOW_SIMPLE 0 ce->state->fence_size
NO_OVERFLOW_SIMPLE 0 ce->state->size
HALF_LOCKED2 0 ce->ring->vma->obj->base.resv
HALF_LOCKED2 0 ce->state->obj->base.resv
HALF_LOCKED2 0 ce->timeline->hwsp_ggtt->obj->base.resv
HALF_LOCKED2 0 &ce->pin_mutex

drivers/gpu/drm/i915/gt/intel_lrc.c lrc_init_state() -> context_wa_bb_offset()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
PARAM_VALUE 0 ce->wa_bb_page 1-255
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce->timeline (-1),728
BUF_SIZE 0 ce->vm (-1),1208
CAPPED_DATA 0 ce->ring->vma 1
DATA_SOURCE 0 ce $0
STR_LEN 0 ce (-1),3,6-7,11,14,17
STR_LEN 0 ce (-1),3,6-7,11,14,17
STR_LEN 0 ce->engine (-1),3,6-7,11,14,17
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 ce->engine->execlists.reset_ccid 0-u32max
HOST_DATA 0 ce->engine->gt->i915->uncore.fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->gt->uc.guc.mmio_msg 0
HOST_DATA 0 ce->engine->gt->uncore->fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->uncore->fifo_count 0-127,u32max
NO_OVERFLOW_SIMPLE 0 ce->ring->effective_size
NO_OVERFLOW_SIMPLE 0 ce->ring->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->fence_size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->obj->base.size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->vm->total
NO_OVERFLOW_SIMPLE 0 ce->ring_size
NO_OVERFLOW_SIMPLE 0 ce->state->fence_size
NO_OVERFLOW_SIMPLE 0 ce->state->size
LOCK2 0 ce->ring->vma->obj->base.resv
LOCK2 0 ce->timeline->hwsp_ggtt->obj->base.resv
HALF_LOCKED2 &gt->perf.lock
HALF_LOCKED2 &pxp->tee_mutex
HALF_LOCKED2 __flags
HALF_LOCKED2 pkt->bb_vma->obj->base.resv
HALF_LOCKED2 pkt->heci_pkt_vma->obj->base.resv
HALF_LOCKED2 scratch->obj->base.resv
HALF_LOCKED2 0 ce->state->obj->base.resv
HALF_LOCKED2 0 &ce->pin_mutex

drivers/gpu/drm/i915/gt/intel_lrc.c lrc_init_state() -> context_wa_bb_offset()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
PARAM_VALUE 0 ce->wa_bb_page 1-255
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce->timeline (-1),728
BUF_SIZE 0 ce->vm (-1),1208
CAPPED_DATA 0 ce->ring->vma 1
DATA_SOURCE 0 ce $0
STR_LEN 0 ce (-1),3,6-7,11,14,17
STR_LEN 0 ce (-1),3,6-7,11,14,17
STR_LEN 0 ce->engine (-1),3,6-7,11,14,17
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 ce->engine->execlists.reset_ccid 0-u32max
HOST_DATA 0 ce->engine->gt->i915->uncore.fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->gt->uc.guc.mmio_msg 0
HOST_DATA 0 ce->engine->gt->uncore->fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->uncore->fifo_count 0-127,u32max
NO_OVERFLOW_SIMPLE 0 ce->ring->effective_size
NO_OVERFLOW_SIMPLE 0 ce->ring->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->fence_size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->obj->base.size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->vm->total
NO_OVERFLOW_SIMPLE 0 ce->ring_size
NO_OVERFLOW_SIMPLE 0 ce->state->fence_size
NO_OVERFLOW_SIMPLE 0 ce->state->size
LOCK2 0 ce->ring->vma->obj->base.resv
LOCK2 0 ce->timeline->hwsp_ggtt->obj->base.resv
HALF_LOCKED2 &gt->perf.lock
HALF_LOCKED2 &pxp->tee_mutex
HALF_LOCKED2 __flags
HALF_LOCKED2 pkt->bb_vma->obj->base.resv
HALF_LOCKED2 pkt->heci_pkt_vma->obj->base.resv
HALF_LOCKED2 scratch->obj->base.resv
HALF_LOCKED2 0 ce->state->obj->base.resv
HALF_LOCKED2 0 &ce->pin_mutex

drivers/gpu/drm/i915/gt/intel_lrc.c lrc_init_state() -> context_wa_bb_offset()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
PARAM_VALUE 0 ce->wa_bb_page 1-255
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce->timeline (-1),728
BUF_SIZE 0 ce->vm (-1),1208
CAPPED_DATA 0 ce->ring->vma 1
DATA_SOURCE 0 ce $0
STR_LEN 0 ce (-1),3,6-7,11,14,17
STR_LEN 0 ce (-1),3,6-7,11,14,17
STR_LEN 0 ce->engine (-1),3,6-7,11,14,17
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 ce->engine->execlists.reset_ccid 0-u32max
HOST_DATA 0 ce->engine->gt->i915->uncore.fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->gt->uc.guc.mmio_msg 0
HOST_DATA 0 ce->engine->gt->uncore->fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->uncore->fifo_count 0-127,u32max
NO_OVERFLOW_SIMPLE 0 ce->ring->effective_size
NO_OVERFLOW_SIMPLE 0 ce->ring->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->fence_size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->obj->base.size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->vm->total
NO_OVERFLOW_SIMPLE 0 ce->ring_size
NO_OVERFLOW_SIMPLE 0 ce->state->fence_size
NO_OVERFLOW_SIMPLE 0 ce->state->size
LOCK2 0 ce->ring->vma->obj->base.resv
LOCK2 0 ce->timeline->hwsp_ggtt->obj->base.resv
HALF_LOCKED2 &gt->perf.lock
HALF_LOCKED2 &pxp->tee_mutex
HALF_LOCKED2 __flags
HALF_LOCKED2 pkt->bb_vma->obj->base.resv
HALF_LOCKED2 pkt->heci_pkt_vma->obj->base.resv
HALF_LOCKED2 scratch->obj->base.resv
HALF_LOCKED2 0 ce->state->obj->base.resv
HALF_LOCKED2 0 &ce->pin_mutex