Defined in 1 files as a prototype:
Defined in 1 files as a function:
Referenced in 12 files:
- drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c, line 121
- drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c, line 113
- drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c, line 124
- drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c, line 131
- drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c, line 127
- drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c, line 133
- drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c, line 136
- drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c, line 144
- drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c, line 152
- drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c, line 141
- drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c, line 140
- drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c, line 141
Smatch caller information:
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn10/dcn10_hwseq.c dcn10_program_pipe() -> (struct hwseq_private_funcs)->setup_vupdate_interrupt()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->current_state | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq->funcs.setup_vupdate_interrupt | 1-u64max |
| PARAM_VALUE | 0 | dc->res_pool | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->force_pstate_change_control | 0,2796816337411768320 |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->program_det_segments | 0,440092313918779392 |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->program_det_size | 0,3324494803509547008,8166695353123938304 |
| PARAM_VALUE | 0 | dc->res_pool->mpc->funcs->get_mpcc_for_dpp_from_secondary | 0 |
| PARAM_VALUE | 0 | dc->res_pool->mpc->funcs->remove_mpcc_from_secondary | 0 |
| PARAM_VALUE | 0 | dc->res_pool->pipe_count | 1-u32max |
| PARAM_VALUE | 0 | dc->res_pool->res_cap->num_dwb | 0-1 |
| PARAM_VALUE | 1 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->degamma_params.rgb_resulted->delta_blue_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->degamma_params.rgb_resulted->delta_green_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->degamma_params.rgb_resulted->delta_red_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->regamma_params.rgb_resulted->delta_blue_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->regamma_params.rgb_resulted->delta_green_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->regamma_params.rgb_resulted->delta_red_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->shaper_params.rgb_resulted->delta_blue_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->shaper_params.rgb_resulted->delta_green_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->shaper_params.rgb_resulted->delta_red_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.hubp->funcs->hubp_wait_pipe_read_start | 0,8092735316039704576 |
| PARAM_VALUE | 1 | pipe_ctx->plane_state | 0,4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe | 0 |
| CAPPED_DATA | 0 | dc->res_pool->pipe_count | 1 |
| DATA_SOURCE | 0 | dc | $0 |
| DATA_SOURCE | 1 | pipe_ctx | $1 |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn20/dcn20_hwseq.c dcn20_program_tg() -> (struct hwseq_private_funcs)->setup_vupdate_interrupt()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->current_state->bw_ctx.dml.vba.DPPCLKUsingSingleDPPChroma | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | dc->current_state->bw_ctx.dml.vba.DPPCLKUsingSingleDPPLuma | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | dc->current_state->res_ctx.pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->funcs->prepare_mcache_programming | 0,804463396097511424,929829862513430528,8759039014133256192 |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->force_pstate_change_control | 0,2796816337411768320 |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->program_det_segments | 0,440092313918779392 |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->program_det_size | 0,3324494803509547008,8166695353123938304 |
| PARAM_VALUE | 0 | dc->res_pool->pipe_count | 1-u32max |
| PARAM_VALUE | 1 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.hubp->funcs->hubp_wait_pipe_read_start | 0,8092735316039704576 |
| PARAM_VALUE | 1 | pipe_ctx->prev_odm_pipe | 0 |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe | 0 |
| PARAM_VALUE | 1 | pipe_ctx->update_flags.bits.global_sync | 1 |
| DATA_SOURCE | 0 | dc | $0 |
| DATA_SOURCE | 1 | pipe_ctx | $1 |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn20/dcn20_hwseq.c dcn20_update_bandwidth() -> (struct hwseq_private_funcs)->setup_vupdate_interrupt()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->pipe_count | 1-u32max |
| PARAM_VALUE | 1 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->plane_state | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe | 0 |
| DATA_SOURCE | 0 | dc | $0 |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn60/dcn60_hwseq.c dcn60_apply_single_controller_ctx_to_hw() -> (struct hwseq_private_funcs)->setup_vupdate_interrupt()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq->funcs.setup_vupdate_interrupt | 1-u64max |
| PARAM_VALUE | 1 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.audio | 0,4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.audio->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.audio->funcs->az_disable_hbr_audio | 5077894766283632640 |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.opp | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.opp->funcs | 4096-ptr_max |
| DATA_SOURCE | 0 | dc | $2 |
| DATA_SOURCE | 1 | pipe_ctx | $0 |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dce110/dce110_hwseq.c dce110_apply_single_controller_ctx_to_hw() -> (struct hwseq_private_funcs)->setup_vupdate_interrupt()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->current_state->res_ctx.pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->fbc_compressor->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq->funcs.setup_vupdate_interrupt | 1-u64max |
| PARAM_VALUE | 0 | dc->res_pool | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->pipe_count | 1-u32max |
| PARAM_VALUE | 1 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->prev_odm_pipe | 0 |
| PARAM_VALUE | 1 | pipe_ctx->stream | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream->link | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.audio | 0,4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.audio->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.audio->funcs->az_disable_hbr_audio | 5077894766283632640 |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.opp | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.opp->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe | 0 |
| CAPPED_DATA | 1 | pipe_ctx->stream | 1 |
| DATA_SOURCE | 0 | dc | $2 |
| DATA_SOURCE | 1 | pipe_ctx | $0 |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn401/dcn401_hwseq.c dcn401_program_tg() -> (struct hwseq_private_funcs)->setup_vupdate_interrupt()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->prev_odm_pipe | 0 |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe | 0 |
| PARAM_VALUE | 1 | pipe_ctx->update_flags.bits.global_sync | 1 |
| DATA_SOURCE | 0 | dc | $0 |
| DATA_SOURCE | 1 | pipe_ctx | $1 |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn401/dcn401_hwseq.c dcn401_update_bandwidth() -> (struct hwseq_private_funcs)->setup_vupdate_interrupt()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->pipe_count | 1-u32max |
| PARAM_VALUE | 1 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->plane_state | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe | 0 |
| DATA_SOURCE | 0 | dc | $0 |
| NOCHECK_CALL |