Defined in 1 files as a prototype:
Defined in 1 files as a function:
Referenced in 1 files:
Smatch caller information:
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn401/dcn401_hwseq.c dcn401_program_pipe_sequence() -> (struct hwseq_private_funcs)->blank_pixel_data_sequence()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq->funcs.blank_pixel_data_sequence | 1-u64max |
| PARAM_VALUE | 1 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->plane_state | 0,4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->prev_odm_pipe | 0 |
| PARAM_VALUE | 1 | pipe_ctx->stream | 1-u64max |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe | 0 |
| DATA_SOURCE | 0 | dc | $0 |
| DATA_SOURCE | 1 | pipe_ctx | $1 |
| DATA_SOURCE | 3 | seq_state | $3 |
| CONTAINER | 0 | -112-56-219720+0 | $(-1) |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn401/dcn401_hwseq.c dcn401_update_odm_sequence() -> (struct hwseq_private_funcs)->blank_pixel_data_sequence()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq->funcs.blank_pixel_data_sequence | 1-u64max |
| PARAM_VALUE | 0 | dc->hwseq->funcs.update_odm_sequence | 1-u64max |
| PARAM_VALUE | 1 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_dlg_sys_param.deepsleep_dcfclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_dlg_sys_param.mem_trip_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_dlg_sys_param.t_extra_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_dlg_sys_param.t_mclk_wm_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_dlg_sys_param.t_sr_wm_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_dlg_sys_param.t_urg_wm_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_dlg_sys_param.total_flip_bw | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_input.clks_cfg.dcfclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_input.clks_cfg.dispclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_input.clks_cfg.dppclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_input.clks_cfg.refclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_input.clks_cfg.socclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_input.dout.output_bpp | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_input.dout.wb.wb_hratio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_input.dout.wb.wb_vratio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_input.pipe.dest.pixel_rate_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_input.pipe.src.dcc_fraction_of_zs_req_chroma | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_input.pipe.src.dcc_fraction_of_zs_req_luma | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->pipe_dlg_param.pixel_rate_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->stream | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream->ctx | 4096-ptr_max |
| PARAM_VALUE | 2 | blank | 1 |
| PARAM_VALUE | 3 | seq_state | 4096-ptr_max |
| PARAM_VALUE | 3 | seq_state->num_steps | 4096-ptr_max |
| DATA_SOURCE | 0 | dc | $0 |
| DATA_SOURCE | 1 | pipe_ctx | $2 |
| DATA_SOURCE | 3 | seq_state | $3 |
| CONTAINER | 0 | -112-56-219720+0 | $(-1) |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_hw_sequencer.c hwss_build_full_sequence() -> (struct hwseq_private_funcs)->blank_pixel_data_sequence()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->current_state | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->current_state->res_ctx.pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq->funcs.blank_pixel_data_sequence | 1-u64max |
| PARAM_VALUE | 0 | dc->res_pool | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->force_pstate_change_control | 0,2796816337411768320 |
| PARAM_VALUE | 0 | dc->res_pool->pipe_count | 1-u32max |
| PARAM_VALUE | 1 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 2 | blank | 1 |
| PARAM_VALUE | 3 | seq_state | 7088695160850235392 |
| PARAM_VALUE | 3 | seq_state->num_steps | 4096-ptr_max |
| CAPPED_DATA | 0 | dc->res_pool->pipe_count | 1 |
| DATA_SOURCE | 0 | dc | $0 |
| CONTAINER | 0 | -112-56-219720+0 | $(-1) |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_hw_sequencer.c hwss_build_full_sequence() -> (struct hwseq_private_funcs)->blank_pixel_data_sequence()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq->funcs.blank_pixel_data_sequence | 1-u64max |
| PARAM_VALUE | 0 | dc->res_pool | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->force_pstate_change_control | 0,2796816337411768320 |
| PARAM_VALUE | 0 | dc->res_pool->pipe_count | 1-u32max |
| PARAM_VALUE | 1 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->prev_odm_pipe | 0 |
| PARAM_VALUE | 1 | pipe_ctx->stream | 1-u64max |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe | 0 |
| PARAM_VALUE | 2 | blank | 1 |
| PARAM_VALUE | 3 | seq_state | 7088695160850235392 |
| PARAM_VALUE | 3 | seq_state->num_steps | 4096-ptr_max |
| CAPPED_DATA | 0 | dc->res_pool->pipe_count | 1 |
| DATA_SOURCE | 0 | dc | $0 |
| CONTAINER | 0 | -112-56-219720+0 | $(-1) |
| NOCHECK_CALL |