Defined in 1 files as a function:
Referenced in 1 files:
Smatch caller information:
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c dcn401_build_clock_update_for_bls() -> dcn401_build_update_display_clocks_sequence()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | clk_mgr_base | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->ctx->dc | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs->build_clock_update_for_bls | 3074158536812285952 |
| PARAM_VALUE | 1 | context | 4096-ptr_max |
| PARAM_VALUE | 2 | new_clocks | 4096-ptr_max |
| PARAM_VALUE | 4 | num_steps_start | 0-14 |
| CAPPED_DATA | 1 | context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz | 1 |
| CAPPED_DATA | 1 | context->bw_ctx.bw.dcn.clk.dramclk_khz | 1 |
| CAPPED_DATA | 1 | context->bw_ctx.bw.dcn.clk.fclk_khz | 1 |
| CAPPED_DATA | 1 | context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching | 1 |
| CAPPED_DATA | 1 | context->bw_ctx.bw.dcn.clk.idle_dramclk_khz | 1 |
| CAPPED_DATA | 1 | context->bw_ctx.bw.dcn.clk.idle_fclk_khz | 1 |
| CAPPED_DATA | 1 | context->bw_ctx.bw.dcn.clk.num_ways | 1 |
| CAPPED_DATA | 1 | context->bw_ctx.bw.dcn.clk.socclk_khz | 1 |
| CAPPED_DATA | 1 | context->bw_ctx.bw.dcn.clk.subvp_prefetch_dramclk_khz | 1 |
| CAPPED_DATA | 1 | context->bw_ctx.bw.dcn.clk.subvp_prefetch_fclk_khz | 1 |
| CAPPED_DATA | 1 | context->stream_count | 1 |
| DATA_SOURCE | 0 | clk_mgr_base | $0 |
| DATA_SOURCE | 1 | context | $1 |
| DATA_SOURCE | 3 | safe_to_lower | $2 |
| DATA_SOURCE | 4 | num_steps_start | r dcn401_build_update_bandwidth_clocks_sequence |
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c dcn401_update_clocks() -> dcn401_build_update_display_clocks_sequence()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | clk_mgr_base | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->ctx->dc | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs->get_clock | 0,1185672433473220608 |
| PARAM_VALUE | 0 | clk_mgr_base->funcs->get_dispclk_from_dentist | 0,2073416932931796992,2887665452536954880,7941745217211535360 |
| PARAM_VALUE | 0 | clk_mgr_base->funcs->update_clocks | 4096-ptr_max |
| PARAM_VALUE | 1 | context | 4096-ptr_max |
| PARAM_VALUE | 2 | new_clocks | 4096-ptr_max |
| PARAM_VALUE | 4 | num_steps_start | 0 |
| BUF_SIZE | 1 | context | (-1),370336 |
| BUF_SIZE | 1 | context | (-1),370336 |
| CAPPED_DATA | 1 | context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz | 1 |
| CAPPED_DATA | 1 | context->bw_ctx.bw.dcn.clk.dramclk_khz | 1 |
| CAPPED_DATA | 1 | context->bw_ctx.bw.dcn.clk.fclk_khz | 1 |
| CAPPED_DATA | 1 | context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching | 1 |
| CAPPED_DATA | 1 | context->bw_ctx.bw.dcn.clk.idle_dramclk_khz | 1 |
| CAPPED_DATA | 1 | context->bw_ctx.bw.dcn.clk.idle_fclk_khz | 1 |
| CAPPED_DATA | 1 | context->bw_ctx.bw.dcn.clk.num_ways | 1 |
| CAPPED_DATA | 1 | context->bw_ctx.bw.dcn.clk.socclk_khz | 1 |
| CAPPED_DATA | 1 | context->bw_ctx.bw.dcn.clk.subvp_prefetch_dramclk_khz | 1 |
| CAPPED_DATA | 1 | context->bw_ctx.bw.dcn.clk.subvp_prefetch_fclk_khz | 1 |
| CAPPED_DATA | 1 | context->stream_count | 1 |
| DATA_SOURCE | 0 | clk_mgr_base | $0 |
| DATA_SOURCE | 1 | context | $1 |
| DATA_SOURCE | 3 | safe_to_lower | $2 |
| RX_PATH | |||
| TASK_NOT_RUNNING |