dml21_build_fams2_programming identifier - Linux source code next-20260811

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linux

Versions

FIXME
- FIXME
  - next-20260811

Defined in 1 files as a prototype:

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h, line 47 (as a prototype)

Defined in 1 files as a function:

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c, line 498 (as a function)

Referenced in 1 files:

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c
- line 244
- line 283

Smatch caller information:

drivers/gpu/drm/amd/amdgpu/../display/dc/dml2_0/dml21/dml21_wrapper_fpu.c dml21_mode_check_and_programming() -> dml21_build_fams2_programming()

Type	Parameter	Key	Value
PARAM_VALUE	0	dc	4096-ptr_max
PARAM_VALUE	0	dc->res_pool	4096-ptr_max
PARAM_VALUE	0	dc->res_pool->funcs	4096-ptr_max
PARAM_VALUE	0	dc->res_pool->funcs->link_encs_assign	0,5262900683136417792
PARAM_VALUE	0	dc->res_pool->funcs->patch_unknown_plane_state	0,4540318623413260288,5832954108700545024,6068615779169501184,6300033728729010176,6488113995699130368
PARAM_VALUE	0	dc->res_pool->funcs->validate_global	0,2747815138363842560,4183144574207725568,5517817891139301376,6058639850796613632
PARAM_VALUE	0	dc->res_pool->res_cap->num_dig_link_enc	0,3,5
PARAM_VALUE	1	context	4096-ptr_max
PARAM_VALUE	1	context->bw_ctx.bw.dcn.clk.dtbclk_en	0
PARAM_VALUE	1	context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support	1
PARAM_VALUE	1	context->bw_ctx.bw.dcn.clk.p_state_change_support	1
PARAM_VALUE	1	context->bw_ctx.bw.dcn.clk.stutter_efficiency.base_efficiency	1
PARAM_VALUE	1	context->bw_ctx.bw.dcn.clk.stutter_efficiency.low_power_efficiency	1
PARAM_VALUE	1	context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_efficiency	1
PARAM_VALUE	1	context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_period	100000
PARAM_VALUE	1	context->bw_ctx.bw.dcn.clk.zstate_support	1
PARAM_VALUE	1	context->stream_count	0
PARAM_VALUE	2	dml_ctx	4096-ptr_max
PARAM_VALUE	2	dml_ctx->architecture	1
CAPPED_DATA	0	dc->res_pool->res_cap->num_dig_link_enc	1
DATA_SOURCE	0	dc	$0
DATA_SOURCE	1	context	$1
DATA_SOURCE	2	dml_ctx	$2
MEM_ZERO	2	&dml_ctx->v21.display_config
MEM_ZERO	2	&dml_ctx->v21.dml_to_dc_pipe_mapping
PREEMPT_ADD
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/dc/dml2_0/dml21/dml21_wrapper_fpu.c dml21_mode_check_and_programming() -> dml21_build_fams2_programming()

Type	Parameter	Key	Value
PARAM_VALUE	0	dc	4096-ptr_max
PARAM_VALUE	0	dc->dml.vba.DPPCLKUsingSingleDPPChroma	-1.797693e+308-1.797693e+308
PARAM_VALUE	0	dc->dml.vba.DPPCLKUsingSingleDPPLuma	-1.797693e+308-1.797693e+308
PARAM_VALUE	0	dc->res_pool	4096-ptr_max
PARAM_VALUE	0	dc->res_pool->funcs	4096-ptr_max
PARAM_VALUE	0	dc->res_pool->funcs->link_encs_assign	0,5262900683136417792
PARAM_VALUE	0	dc->res_pool->funcs->patch_unknown_plane_state	0,4540318623413260288,5832954108700545024,6068615779169501184,6300033728729010176,6488113995699130368
PARAM_VALUE	0	dc->res_pool->funcs->validate_global	0,2747815138363842560,4183144574207725568,5517817891139301376,6058639850796613632
PARAM_VALUE	0	dc->res_pool->res_cap->num_dig_link_enc	0,3,5
PARAM_VALUE	1	context	4096-ptr_max
PARAM_VALUE	1	context->bw_ctx.bw.dcn.clk.dppclk_khz	0-s32max
PARAM_VALUE	1	context->bw_ctx.bw.dcn.clk.zstate_support	0-1
PARAM_VALUE	1	*context->res_ctx.is_dsc_acquired	0-1
PARAM_VALUE	2	dml_ctx	4096-ptr_max
PARAM_VALUE	2	dml_ctx->architecture	1
PARAM_VALUE	2	dml_ctx->config.skip_hw_state_mapping	0
PARAM_VALUE	2	dml_ctx->v21.display_config.gpuvm_max_page_table_levels	1-u32max
PARAM_VALUE	2	dml_ctx->v21.display_config.minimize_det_reallocation	1
PARAM_VALUE	2	dml_ctx->v21.display_config.num_planes	1-s32max
PARAM_VALUE	2	dml_ctx->v21.display_config.num_streams	1-s32max
PARAM_VALUE	2	dml_ctx->v21.display_config.overrides.all_streams_blanked	1
PARAM_VALUE	2	dml_ctx->v21.display_config.overrides.enable_subvp_implicit_pmo	1
PARAM_VALUE	2	dml_ctx->v21.display_config.overrides.hw.force_unbounded_requesting.enable	1
PARAM_VALUE	2	dml_ctx->v21.mode_programming.dml2_instance	4096-ptr_max
PARAM_VALUE	2	dml_ctx->v21.mode_programming.dml2_instance->funcs.build_mode_programming	0,7150732188596219904
PARAM_VALUE	2	dml_ctx->v21.mode_programming.programming	4096-ptr_max
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.bottom_pipe->dml_dlg_sys_param.deepsleep_dcfclk_mhz	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.bottom_pipe->dml_dlg_sys_param.mem_trip_us	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.bottom_pipe->dml_dlg_sys_param.t_extra_us	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.bottom_pipe->dml_dlg_sys_param.t_mclk_wm_us	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.bottom_pipe->dml_dlg_sys_param.t_sr_wm_us	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.bottom_pipe->dml_dlg_sys_param.t_urg_wm_us	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.bottom_pipe->dml_dlg_sys_param.total_flip_bw	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.bottom_pipe->dml_input.clks_cfg.dcfclk_mhz	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.bottom_pipe->dml_input.clks_cfg.dispclk_mhz	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.bottom_pipe->dml_input.clks_cfg.dppclk_mhz	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.bottom_pipe->dml_input.clks_cfg.refclk_mhz	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.bottom_pipe->dml_input.clks_cfg.socclk_mhz	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.bottom_pipe->dml_input.dout.output_bpp	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.bottom_pipe->dml_input.dout.wb.wb_hratio	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.bottom_pipe->dml_input.dout.wb.wb_vratio	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.bottom_pipe->dml_input.pipe.dest.pixel_rate_mhz	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.bottom_pipe->dml_input.pipe.scale_ratio_depth.vinit	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.bottom_pipe->dml_input.pipe.scale_ratio_depth.vinit_c	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.bottom_pipe->pipe_dlg_param.pixel_rate_mhz	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.dml_dlg_sys_param.deepsleep_dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.dml_dlg_sys_param.mem_trip_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.dml_dlg_sys_param.t_extra_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.dml_dlg_sys_param.t_mclk_wm_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.dml_dlg_sys_param.t_sr_wm_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.dml_dlg_sys_param.t_urg_wm_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.dml_dlg_sys_param.total_flip_bw	-9.223372e+18-9.223372e+18
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.dml_input.clks_cfg.dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.dml_input.clks_cfg.dispclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.dml_input.clks_cfg.dppclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.dml_input.clks_cfg.refclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.dml_input.clks_cfg.socclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.dml_input.dout.output_bpp	-9.223372e+18-9.223372e+18
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.dml_input.dout.wb.wb_hratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.dml_input.dout.wb.wb_vratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.dest.pixel_rate_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.hscl_ratio_c	-9.223372e+18-9.223372e+18
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.vinit	-9.223372e+18-9.223372e+18
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.vinit_bot	-9.223372e+18-9.223372e+18
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.vinit_bot_c	-9.223372e+18-9.223372e+18
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.vinit_c	-9.223372e+18-9.223372e+18
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.vscl_ratio_c	-9.223372e+18-9.223372e+18
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.src.dcc_fraction_of_zs_req_chroma	-9.223372e+18-9.223372e+18
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.src.dcc_fraction_of_zs_req_luma	-9.223372e+18-9.223372e+18
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.pipe_dlg_param.pixel_rate_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.plane_res.spl_in.basic_in.format	0-9
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.plane_res.spl_in.basic_in.mpc_h_slice_index	0-s32max
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.plane_res.spl_in.debug.visual_confirm_base_offset	0-10
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.plane_res.spl_in.odm_slice_index	0-s32max
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.plane_res.spl_out.dscl_prog_data->dscl_mode	1,3
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.plane_res.spl_out.dscl_prog_data->isharp_fmt.mode	0-1
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.plane_res.spl_out.dscl_prog_data->isharp_fmt.norm	15360
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.plane_res.spl_out.dscl_prog_data->ratios.h_scale_ratio	0,32-134217696
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.plane_res.spl_out.dscl_prog_data->ratios.v_scale_ratio	0,32-134217696
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.top_pipe->dml_dlg_sys_param.deepsleep_dcfclk_mhz	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.top_pipe->dml_dlg_sys_param.mem_trip_us	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.top_pipe->dml_dlg_sys_param.t_extra_us	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.top_pipe->dml_dlg_sys_param.t_mclk_wm_us	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.top_pipe->dml_dlg_sys_param.t_sr_wm_us	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.top_pipe->dml_dlg_sys_param.t_urg_wm_us	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.top_pipe->dml_dlg_sys_param.total_flip_bw	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.top_pipe->dml_input.clks_cfg.dcfclk_mhz	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.top_pipe->dml_input.clks_cfg.dispclk_mhz	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.top_pipe->dml_input.clks_cfg.dppclk_mhz	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.top_pipe->dml_input.clks_cfg.refclk_mhz	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.top_pipe->dml_input.clks_cfg.socclk_mhz	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.top_pipe->dml_input.dout.output_bpp	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.top_pipe->dml_input.dout.wb.wb_hratio	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.top_pipe->dml_input.dout.wb.wb_vratio	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.top_pipe->dml_input.pipe.dest.pixel_rate_mhz	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.top_pipe->dml_input.pipe.scale_ratio_depth.hscl_ratio	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.top_pipe->dml_input.pipe.scale_ratio_depth.vinit	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.top_pipe->dml_input.pipe.scale_ratio_depth.vinit_bot	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.top_pipe->dml_input.pipe.scale_ratio_depth.vinit_bot_c	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.top_pipe->dml_input.pipe.scale_ratio_depth.vinit_c	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.top_pipe->dml_input.pipe.scale_ratio_depth.vscl_ratio	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	dml_ctx->v21.scratch.temp_pipe.top_pipe->pipe_dlg_param.pixel_rate_mhz	-1.797693e+308-1.797693e+308
PARAM_VALUE	2	*dml_ctx->v21.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid	1
PARAM_VALUE	2	*dml_ctx->v21.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id	0-4294967295
PARAM_VALUE	2	*dml_ctx->v21.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid	1
PARAM_VALUE	2	*dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id	0-4294967295
PARAM_VALUE	2	*dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid	0-1
PARAM_VALUE	2	*dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id	0-4294967295
PARAM_VALUE	2	*dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid	0-1
PARAM_VALUE	2	*dml_ctx->v21.scratch.temp_pipe->plane_res.spl_out->dscl_prog_data->isharp_delta	0-4294967295
CAPPED_DATA	0	dc->res_pool->pipe_count	1
CAPPED_DATA	0	dc->res_pool->res_cap->num_dig_link_enc	1
CAPPED_DATA	2	dml_ctx->v21.mode_programming.programming->global_regs.num_watermark_sets	1
DATA_SOURCE	0	dc	$0
DATA_SOURCE	1	context	$1
DATA_SOURCE	2	dml_ctx	$2
MEM_ZERO	2	&dml_ctx->v21.display_config
MEM_ZERO	2	&dml_ctx->v21.dml_to_dc_pipe_mapping
PREEMPT_ADD
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL