Defined in 1 files as a prototype:
Defined in 1 files as a function:
Referenced in 6 files:
- drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c, line 569
- drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c, line 403
- drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c, line 287
- drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c, line 1524
- drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c, line 134
- drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c, line 249
Smatch caller information:
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn35/dcn35_hwseq.c dcn35_enable_plane() -> (struct dpp_funcs)->dpp_dppclk_control()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dpp_base | 4096-ptr_max |
| PARAM_VALUE | 0 | dpp_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | dppclk_div | 0 |
| PARAM_VALUE | 2 | enable | 1 |
| CONTAINER | 0 | -232-0+0 | $(-1) |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn35/dcn35_hwseq.c dcn35_plane_atomic_disable() -> (struct dpp_funcs)->dpp_dppclk_control()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dpp_base | 4096-ptr_max |
| PARAM_VALUE | 0 | dpp_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | dppclk_div | 0 |
| PARAM_VALUE | 2 | enable | 0 |
| CONTAINER | 0 | -232-0+0 | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn50/dcn50_hwseq.c dcn50_update_dchubp_dpp() -> (struct dpp_funcs)->dpp_dppclk_control()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dpp_base | 4096-ptr_max |
| PARAM_VALUE | 0 | dpp_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | dppclk_div | 0 |
| PARAM_VALUE | 2 | enable | 1 |
| CONTAINER | 0 | -232-0+0 | $(-1) |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c ramp_up_dispclk_with_dpp() -> (struct dpp_funcs)->dpp_dppclk_control()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dpp_base | 4096-ptr_max |
| PARAM_VALUE | 0 | dpp_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 2 | enable | 1 |
| CONTAINER | 0 | *(-232-0+0) | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn10/dcn10_hwseq.c dcn10_plane_atomic_disable() -> (struct dpp_funcs)->dpp_dppclk_control()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dpp_base | 4096-ptr_max |
| PARAM_VALUE | 0 | dpp_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | dppclk_div | 0 |
| PARAM_VALUE | 2 | enable | 0 |
| CONTAINER | 0 | -232-0+0 | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn10/dcn10_hwseq.c dcn10_update_dchubp_dpp() -> (struct dpp_funcs)->dpp_dppclk_control()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dpp_base | 4096-ptr_max |
| PARAM_VALUE | 0 | dpp_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 2 | enable | 1 |
| CONTAINER | 0 | -232-0+0 | $(-1) |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn20/dcn20_hwseq.c dcn20_plane_atomic_disable() -> (struct dpp_funcs)->dpp_dppclk_control()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dpp_base | 4096-ptr_max |
| PARAM_VALUE | 0 | dpp_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | dppclk_div | 0 |
| PARAM_VALUE | 2 | enable | 0 |
| CONTAINER | 0 | -232-0+0 | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_hw_sequencer.c hwss_dpp_dppclk_control() -> (struct dpp_funcs)->dpp_dppclk_control()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dpp_base | 4096-ptr_max |
| PARAM_VALUE | 0 | dpp_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dpp_base->funcs->dpp_dppclk_control | 8534821316371431424,8807426702212612096 |
| PARAM_VALUE | 1 | dppclk_div | 0 |
| CONTAINER | 0 | -232-0+0 | $(-1) |
| NOCHECK_CALL |