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Documented in 1 files:

Defined in 1 files as a prototype:

Defined in 1 files as a function:

Referenced in 2 files:

Smatch caller information:

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c dpu_encoder_phys_wb_setup() -> dpu_encoder_helper_phys_setup_cdm()

Type Parameter Key Value
PARAM_VALUE 0 phys_enc 4096-ptr_max
PARAM_VALUE 0 phys_enc->cdm_cfg.output_fmt->bpc_a 0-1,3
PARAM_VALUE 0 phys_enc->cdm_cfg.output_fmt->bpc_b_cb 0-1,3
PARAM_VALUE 0 phys_enc->cdm_cfg.output_fmt->bpc_g_y 0-3
PARAM_VALUE 0 phys_enc->cdm_cfg.output_fmt->bpc_r_cr 0-1,3
PARAM_VALUE 0 phys_enc->cdm_cfg.output_fmt->bpp 1-4
PARAM_VALUE 0 phys_enc->cdm_cfg.output_fmt->chroma_sample 0-1,3
PARAM_VALUE 0 phys_enc->cdm_cfg.output_fmt->fetch_mode 0,2
PARAM_VALUE 0 phys_enc->cdm_cfg.output_fmt->fetch_type 0-2
PARAM_VALUE 0 phys_enc->cdm_cfg.output_fmt->flags 8-10,12-15,19
PARAM_VALUE 0 phys_enc->cdm_cfg.output_fmt->num_planes 1-4
PARAM_VALUE 0 phys_enc->cdm_cfg.output_fmt->tile_height 1,4,8
PARAM_VALUE 0 phys_enc->cdm_cfg.output_fmt->unpack_count 1-4
PARAM_VALUE 0 phys_enc->dpu_kms 4096-ptr_max
PARAM_VALUE 0 phys_enc->dpu_kms->catalog 0,4096-ptr_max
PARAM_VALUE 0 phys_enc->dpu_kms->hw_mdp->hw.log_mask 2,4,8,16,32,64,128,256,1024,2048,4096,8192
PARAM_VALUE 0 phys_enc->dpu_kms->hw_vbif 0,4096-ptr_max
PARAM_VALUE 0 phys_enc->dpu_kms->hw_vbif->cap 0-s64max
PARAM_VALUE 0 phys_enc->hw_ctl->hw.log_mask 2,4,8,16,32,64,128,256,1024,2048,4096,8192
PARAM_VALUE 0 phys_enc->hw_ctl->mdss_ver->core_major_ver 1,3-10,12-13
PARAM_VALUE 0 phys_enc->hw_pp->merge_3d->hw.log_mask 2,4,8,16,32,64,128,256,1024,2048,4096,8192
PARAM_VALUE 0 phys_enc->hw_wb 4096-ptr_max
PARAM_VALUE 0 phys_enc->hw_wb->caps 4096-ptr_max
PARAM_VALUE 0 phys_enc->hw_wb->caps->xin_id 6
PARAM_VALUE 0 phys_enc->hw_wb->hw.log_mask 2,4,8,16,32,64,128,256,1024,2048,4096,8192
PARAM_VALUE 0 phys_enc->ops.prepare_for_kickoff 1-u64max
PARAM_VALUE 0 phys_enc->parent 0,4096-ptr_max
PARAM_VALUE 0 *phys_enc->dpu_kms->hw_intr->cache_irq_mask 0-4294967295
PARAM_VALUE 1 dpu_fmt->bpc_a 0-1,3
PARAM_VALUE 1 dpu_fmt->chroma_sample 0-1,3
PARAM_VALUE 2 output_type 1
DATA_SOURCE 0 phys_enc $0
DATA_SOURCE 1 dpu_fmt r msm_framebuffer_format
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
NO_OVERFLOW_SIMPLE 0 phys_enc->cached_mode.clock

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c dpu_encoder_phys_vid_enable() -> dpu_encoder_helper_phys_setup_cdm()

Type Parameter Key Value
PARAM_VALUE 0 phys_enc 4096-ptr_max
PARAM_VALUE 0 phys_enc->dpu_kms->base.dev 0,4096-ptr_max
PARAM_VALUE 0 phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver 0-10,12-13
PARAM_VALUE 0 phys_enc->hw_intf 4096-ptr_max
PARAM_VALUE 0 phys_enc->hw_intf->ops.enable_timing 3538371962127917056
PARAM_VALUE 0 phys_enc->hw_mdptop->hw.log_mask 2,4,8,16,32,64,128,256,1024,2048,4096,8192
PARAM_VALUE 0 phys_enc->ops.enable 1-u64max
PARAM_VALUE 1 dpu_fmt 0
PARAM_VALUE 2 output_type 0
DATA_SOURCE 0 phys_enc $0
DATA_SOURCE 1 dpu_fmt r mdp_get_format
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
LOCK2 &dpu_enc->enc_lock
HALF_LOCKED2 &pool->lock
HALF_LOCKED2 &state->dev->mode_config.connection_mutex
HALF_LOCKED2 &state->dev->mode_config.connection_mutex.mutex
TYPE_LOCK (struct dpu_encoder_virt)->enc_lock