exynos_retention_init identifier - Linux source code next-20260811

Projects

linux

Versions

FIXME
- FIXME
  - next-20260811

Defined in 1 files as a prototype:

drivers/pinctrl/samsung/pinctrl-exynos.h, line 280 (as a prototype)

Defined in 1 files as a function:

drivers/pinctrl/samsung/pinctrl-exynos.c, line 1077 (as a function)

Referenced in 2 files:

Smatch caller information:

drivers/pinctrl/samsung/pinctrl-samsung.c samsung_pinctrl_probe() -> (struct samsung_retention_data)->init()

Type	Parameter	Key	Value
PARAM_VALUE	0	drvdata	4096-ptr_max
PARAM_VALUE	0	drvdata->dev	4096-ptr_max
PARAM_VALUE	0	drvdata->dev->devres_head.prev	4096-ptr_max
PARAM_VALUE	0	drvdata->irq	0-s32max
PARAM_VALUE	0	drvdata->nr_banks	1-11,13-18,20-23,25-26,34-35
PARAM_VALUE	0	drvdata->pin_banks	4096-ptr_max
PARAM_VALUE	0	drvdata->pin_banks->drvdata	0
PARAM_VALUE	0	drvdata->pin_banks->drvdata->nr_banks	1-11,13-18,20-23,25-26,34-35
PARAM_VALUE	0	drvdata->pin_banks->drvdata->pin_banks	4096-ptr_max
PARAM_VALUE	0	drvdata->pin_banks->drvdata->resume	0,3865597856650199040,5682212938563579904,6044946380431929344
PARAM_VALUE	0	drvdata->pin_banks->drvdata->suspend	0,296568234772860928,1525672569433104384,1624438740445720576
PARAM_VALUE	0	drvdata->pin_banks->eint_base	0
PARAM_VALUE	0	drvdata->pin_banks->eint_con_offset	0
PARAM_VALUE	0	drvdata->pin_banks->eint_fltcon_offset	0
PARAM_VALUE	0	drvdata->pin_banks->eint_func	0
PARAM_VALUE	0	drvdata->pin_banks->eint_mask	0
PARAM_VALUE	0	drvdata->pin_banks->eint_mask_offset	0
PARAM_VALUE	0	drvdata->pin_banks->eint_num	0
PARAM_VALUE	0	drvdata->pin_banks->eint_offset	0
PARAM_VALUE	0	drvdata->pin_banks->eint_pend_offset	0
PARAM_VALUE	0	drvdata->pin_banks->eint_type	0
PARAM_VALUE	0	drvdata->pin_banks->fwnode	4096-ptr_max
PARAM_VALUE	0	drvdata->pin_banks->fwnode->ops	4096-ptr_max
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.add_pin_ranges	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.base	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.can_sleep	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.dbg_show	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.direction_input	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.direction_output	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.dis_hw_timestamp	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.en_hw_timestamp	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.free	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.fwnode	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.get	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.get_direction	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.get_multiple	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.gpiodev	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.init_valid_mask	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.child_irq_domain_ops.activate	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.child_irq_domain_ops.alloc	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.child_irq_domain_ops.deactivate	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.child_irq_domain_ops.debug_show	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.child_irq_domain_ops.free	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.child_irq_domain_ops.get_fwspec_info	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.child_irq_domain_ops.map	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.child_irq_domain_ops.match	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.child_irq_domain_ops.select	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.child_irq_domain_ops.translate	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.child_irq_domain_ops.unmap	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.child_irq_domain_ops.xlate	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.child_offset_to_irq	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.child_to_parent_hwirq	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.chip	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.default_type	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.domain	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.domain_is_allocated_externally	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.first	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.fwnode	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.handler	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.init_hw	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.init_valid_mask	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.initialized	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.irq_disable	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.irq_enable	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.irq_mask	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.irq_unmask	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.lock_key	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.map	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.num_parents	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.parent_domain	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.parent_handler	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.parent_handler_data	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.parent_handler_data_array	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.parents	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.per_parent_data	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.populate_parent_alloc_arg	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.request_key	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.threaded	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.irq.valid_mask	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.label	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.names	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.ngpio	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.of_gpio_n_cells	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.of_node_instance_match	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.of_xlate	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.offset	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.owner	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.parent	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.request	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.set	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.set_config	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.set_multiple	0
PARAM_VALUE	0	drvdata->pin_banks->gpio_chip.to_irq	0
PARAM_VALUE	0	drvdata->pin_banks->grange.base	0
PARAM_VALUE	0	drvdata->pin_banks->grange.gc	0
PARAM_VALUE	0	drvdata->pin_banks->grange.id	0
PARAM_VALUE	0	drvdata->pin_banks->grange.name	0
PARAM_VALUE	0	drvdata->pin_banks->grange.node.next	0
PARAM_VALUE	0	drvdata->pin_banks->grange.node.prev	0
PARAM_VALUE	0	drvdata->pin_banks->grange.npins	0
PARAM_VALUE	0	drvdata->pin_banks->grange.pin_base	0
PARAM_VALUE	0	drvdata->pin_banks->grange.pins	0
PARAM_VALUE	0	drvdata->pin_banks->id	0
PARAM_VALUE	0	drvdata->pin_banks->irq_chip	0
PARAM_VALUE	0	drvdata->pin_banks->irq_domain	0
PARAM_VALUE	0	drvdata->pin_banks->name	0
PARAM_VALUE	0	drvdata->pin_banks->nr_pins	0
PARAM_VALUE	0	drvdata->pin_banks->pctl_base	0
PARAM_VALUE	0	drvdata->pin_banks->pctl_offset	0
PARAM_VALUE	0	drvdata->pin_banks->pin_base	0
PARAM_VALUE	0	drvdata->pin_banks->slock.magic	0,3735899821
PARAM_VALUE	0	drvdata->pin_banks->slock.owner	0,(-1)
PARAM_VALUE	0	drvdata->pin_banks->slock.owner_cpu	0,u32max
PARAM_VALUE	0	drvdata->pin_banks->slock.raw_lock.locked	0
PARAM_VALUE	0	drvdata->pin_banks->slock.raw_lock.locked_pending	0
PARAM_VALUE	0	drvdata->pin_banks->slock.raw_lock.pending	0
PARAM_VALUE	0	drvdata->pin_banks->slock.raw_lock.tail	0
PARAM_VALUE	0	drvdata->pin_banks->slock.raw_lock.val.counter	0
PARAM_VALUE	0	drvdata->pin_banks->soc_priv	0
PARAM_VALUE	0	drvdata->pin_banks->type	0
PARAM_VALUE	0	drvdata->resume	0,3865597856650199040,5682212938563579904,6044946380431929344
PARAM_VALUE	0	drvdata->suspend	0,296568234772860928,1525672569433104384,1624438740445720576
PARAM_VALUE	1	data	4096-ptr_max
BUF_SIZE	0	drvdata	232
BUF_SIZE	0	drvdata->dev	1616
DATA_SOURCE	0	drvdata	r devm_kzalloc
FUZZY_MAX	0	drvdata->irq	0
CONTAINER	1	*(-24+0)	$(-1)
MEM_ZERO	0	drvdata
RX_PATH
TASK_NOT_RUNNING
NO_OVERFLOW_SIMPLE	0	drvdata->nr_banks