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Defined in 1 files as a function:

Referenced in 7 files:

Smatch caller information:

drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c intel_context_is_parallel() -> intel_context_is_parent()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
DATA_SOURCE 0 ce $0

drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c intel_context_timeline_lock() -> intel_context_is_parent()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
DATA_SOURCE 0 ce $0
NO_OVERFLOW_SIMPLE 0 ce->ring->effective_size
HALF_LOCKED2 pool->obj->base.resv

drivers/gpu/drm/i915/gt/intel_context.c intel_context_fini() -> intel_context_is_parent()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
DATA_SOURCE 0 ce $0
PREEMPT_ADD
RX_PATH
TASK_NOT_RUNNING

drivers/gpu/drm/i915/gt/intel_context.c intel_context_is_parallel() -> intel_context_is_parent()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce->timeline (-1),728
BUF_SIZE 0 ce->vm (-1),1208
CAPPED_DATA 0 ce->ring->vma 1
DATA_SOURCE 0 ce $0
STR_LEN 0 ce->engine (-1),3,6-7,11,14,17
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 ce->engine->execlists.reset_ccid 0-u32max
HOST_DATA 0 ce->engine->gt->i915->uncore.fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->gt->uc.guc.mmio_msg 0
HOST_DATA 0 ce->engine->gt->uc.guc.timestamp.gt_stamp 0-u64max
HOST_DATA 0 ce->engine->gt->uncore->fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->uncore->fifo_count 0-127,u32max
NO_OVERFLOW_SIMPLE 0 ce->ring->effective_size
NO_OVERFLOW_SIMPLE 0 ce->ring->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->fence_size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->vm->total
NO_OVERFLOW_SIMPLE 0 ce->ring_size
NO_OVERFLOW_SIMPLE 0 ce->state->fence_size
NO_OVERFLOW_SIMPLE 0 ce->state->size
LOCK2 0 ce->ring->vma->obj->base.resv
LOCK2 0 ce->timeline->hwsp_ggtt->obj->base.resv
LOCK2 0 &ce->pin_mutex
HALF_LOCKED2 &gt->perf.lock
HALF_LOCKED2 &pxp->tee_mutex
HALF_LOCKED2 __flags
HALF_LOCKED2 pkt->bb_vma->obj->base.resv
HALF_LOCKED2 pkt->heci_pkt_vma->obj->base.resv
HALF_LOCKED2 scratch->obj->base.resv
HALF_LOCKED2 0 ce->state->obj->base.resv
TYPE_LOCK (struct intel_context)->pin_mutex

drivers/gpu/drm/i915/gt/intel_lrc.c __lrc_alloc_state() -> intel_context_is_parent()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce->timeline (-1),728
BUF_SIZE 0 ce->vm (-1),1208
DATA_SOURCE 0 ce $0
STR_LEN 0 ce (-1),3,6-7,11,14,17
STR_LEN 0 ce (-1),3,6-7,11,14,17
STR_LEN 0 ce->engine (-1),3,6-7,11,14,17
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 ce->engine->execlists.reset_ccid 0-u32max
HOST_DATA 0 ce->engine->gt->i915->uncore.fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->gt->uc.guc.mmio_msg 0
HOST_DATA 0 ce->engine->gt->uncore->fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->uncore->fifo_count 0-127,u32max
NO_OVERFLOW_SIMPLE 0 ce->ring->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->fence_size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->obj->base.size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->vm->total
NO_OVERFLOW_SIMPLE 0 ce->ring_size
NO_OVERFLOW_SIMPLE 0 ce->state->fence_size
NO_OVERFLOW_SIMPLE 0 ce->state->size
LOCK2 0 &ce->pin_mutex
TYPE_LOCK (struct intel_context)->pin_mutex

drivers/gpu/drm/i915/i915_request.c intel_context_is_parallel() -> intel_context_is_parent()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
BUF_SIZE 0 ce (-1),1-s32max
BUF_SIZE 0 ce (-1),1-s32max
DATA_SOURCE 0 ce $0
RX_PATH
TASK_NOT_RUNNING
NO_OVERFLOW_SIMPLE 0 ce->ring_size

drivers/gpu/drm/i915/i915_request.c intel_context_timeline_lock() -> intel_context_is_parent()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce->timeline (-1),728
BUF_SIZE 0 ce->vm (-1),1208
DATA_SOURCE 0 ce $0
STR_LEN 0 ce->engine (-1),3,6
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 ce->engine->execlists.reset_ccid 0-u32max
HOST_DATA 0 ce->engine->gt->i915->uncore.fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->gt->uc.guc.mmio_msg 0
HOST_DATA 0 ce->engine->gt->uc.guc.timestamp.gt_stamp 0-u64max
HOST_DATA 0 ce->engine->gt->uncore->fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->uncore->fifo_count 0-127,u32max
NO_OVERFLOW_SIMPLE 0 ce->ring->effective_size
NO_OVERFLOW_SIMPLE 0 ce->ring->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->fence_size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->vm->total
NO_OVERFLOW_SIMPLE 0 ce->ring_size
NO_OVERFLOW_SIMPLE 0 ce->state->fence_size
NO_OVERFLOW_SIMPLE 0 ce->state->size
HALF_LOCKED2 &ce->pin_mutex
HALF_LOCKED2 &gt->perf.lock
HALF_LOCKED2 &pool->lock
HALF_LOCKED2 &pxp->tee_mutex
HALF_LOCKED2 &vgpu->vgpu_lock
HALF_LOCKED2 __flags
HALF_LOCKED2 batch->obj->base.resv
HALF_LOCKED2 ctx->obj->base.resv
HALF_LOCKED2 obj->base.resv
HALF_LOCKED2 pkt->bb_vma->obj->base.resv
HALF_LOCKED2 pkt->heci_pkt_vma->obj->base.resv
HALF_LOCKED2 rpcs->base.resv
HALF_LOCKED2 scratch->obj->base.resv
HALF_LOCKED2 tl->hwsp_ggtt->obj->base.resv
HALF_LOCKED2 vma->obj->base.resv

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c __guc_add_request() -> intel_context_is_parent()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce (-1)-s32max
DATA_SOURCE 0 ce r request_to_scheduling_context
PREEMPT_ADD <- disables preempt
RX_PATH
TASK_NOT_RUNNING
LOCK2 &sched_engine->lock
LOCK2 flags
LOCK2 0 &ce->guc_state.lock
HALF_LOCKED2 rcu_read
TYPE_LOCK (struct i915_sched_engine)->lock
TYPE_LOCK (struct intel_context)->guc_state.lock

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c __guc_add_request() -> intel_context_is_parent()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce (-1)-s32max
DATA_SOURCE 0 ce r request_to_scheduling_context
PREEMPT_ADD <- disables preempt
RX_PATH
TASK_NOT_RUNNING
LOCK2 &sched_engine->lock
LOCK2 flags
LOCK2 0 &ce->guc_state.lock
HALF_LOCKED2 rcu_read
TYPE_LOCK (struct i915_sched_engine)->lock
TYPE_LOCK (struct intel_context)->guc_state.lock

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c __release_guc_id() -> intel_context_is_parent()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
DATA_SOURCE 0 ce $1
PREEMPT_ADD
RX_PATH
TASK_NOT_RUNNING
LOCK2 &guc->submission_state.lock
HALF_LOCKED2 flags
TYPE_LOCK (struct intel_guc)->submission_state.lock

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c assign_guc_id() -> intel_context_is_parent()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce->timeline (-1),728
BUF_SIZE 0 ce->vm (-1),1208
DATA_SOURCE 0 ce $1
STR_LEN 0 ce->engine (-1),3,6-7,11,14,17
PREEMPT_ADD
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 ce->engine->execlists.reset_ccid 0-u32max
HOST_DATA 0 ce->engine->gt->i915->uncore.fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->gt->uc.guc.mmio_msg 0
HOST_DATA 0 ce->engine->gt->uncore->fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->uncore->fifo_count 0-127,u32max
NO_OVERFLOW_SIMPLE 0 ce->ring->effective_size
NO_OVERFLOW_SIMPLE 0 ce->ring->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->fence_size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->vm->total
NO_OVERFLOW_SIMPLE 0 ce->ring_size
NO_OVERFLOW_SIMPLE 0 ce->state->fence_size
NO_OVERFLOW_SIMPLE 0 ce->state->size
LOCK2 &guc->submission_state.lock
LOCK2 flags
HALF_LOCKED2 __flags
HALF_LOCKED2 0 ce->ring->vma->obj->base.resv
HALF_LOCKED2 0 ce->state->obj->base.resv
HALF_LOCKED2 0 ce->timeline->hwsp_ggtt->obj->base.resv
HALF_LOCKED2 0 &ce->pin_mutex
TYPE_LOCK (struct intel_guc)->submission_state.lock

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c assign_guc_id() -> intel_context_is_parent()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce->timeline (-1),728
BUF_SIZE 0 ce->vm (-1),1208
DATA_SOURCE 0 ce $1
STR_LEN 0 ce->engine (-1),3,6-7,11,14,17
PREEMPT_ADD
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 ce->engine->execlists.reset_ccid 0-u32max
HOST_DATA 0 ce->engine->gt->i915->uncore.fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->gt->uc.guc.mmio_msg 0
HOST_DATA 0 ce->engine->gt->uncore->fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->uncore->fifo_count 0-127,u32max
NO_OVERFLOW_SIMPLE 0 ce->ring->effective_size
NO_OVERFLOW_SIMPLE 0 ce->ring->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->fence_size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->vm->total
NO_OVERFLOW_SIMPLE 0 ce->ring_size
NO_OVERFLOW_SIMPLE 0 ce->state->fence_size
NO_OVERFLOW_SIMPLE 0 ce->state->size
LOCK2 &guc->submission_state.lock
LOCK2 flags
HALF_LOCKED2 __flags
HALF_LOCKED2 0 ce->ring->vma->obj->base.resv
HALF_LOCKED2 0 ce->state->obj->base.resv
HALF_LOCKED2 0 ce->timeline->hwsp_ggtt->obj->base.resv
HALF_LOCKED2 0 &ce->pin_mutex
TYPE_LOCK (struct intel_guc)->submission_state.lock

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c guc_id_pressure() -> intel_context_is_parent()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce->timeline (-1),728
BUF_SIZE 0 ce->vm (-1)-0,1208
DATA_SOURCE 0 ce $1
STR_LEN 0 ce->engine (-1),3,6
STR_LEN 0 ce->gem_context->i915 (-1),1,4
PREEMPT_ADD
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 ce->engine->execlists.reset_ccid 0-u32max
HOST_DATA 0 ce->engine->gt->i915->uncore.fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->gt->uc.guc.mmio_msg 0
HOST_DATA 0 ce->engine->gt->uc.guc.timestamp.gt_stamp 0-u64max
HOST_DATA 0 ce->engine->gt->uncore->fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->uncore->fifo_count 0-127,u32max
NO_OVERFLOW_SIMPLE 0 ce->ring->effective_size
NO_OVERFLOW_SIMPLE 0 ce->ring->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->fence_size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->vm->total
NO_OVERFLOW_SIMPLE 0 ce->ring_size
NO_OVERFLOW_SIMPLE 0 ce->state->fence_size
NO_OVERFLOW_SIMPLE 0 ce->state->size
LOCK2 flags
LOCK2 0 &ce->guc_state.lock
HALF_LOCKED2 &gt->perf.lock
HALF_LOCKED2 &pxp->tee_mutex
HALF_LOCKED2 __flags
HALF_LOCKED2 pkt->bb_vma->obj->base.resv
HALF_LOCKED2 pkt->heci_pkt_vma->obj->base.resv
HALF_LOCKED2 vma->obj->base.resv
HALF_LOCKED2 0 &ce->pin_mutex
HALF_LOCKED2 0 &ce->timeline->mutex
TYPE_LOCK (struct intel_context)->guc_state.lock

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c intel_context_is_parallel() -> intel_context_is_parent()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
DATA_SOURCE 0 ce $0
PREEMPT_ADD
RX_PATH
TASK_NOT_RUNNING
NO_OVERFLOW_SIMPLE 0 ce->ring_size
LOCK2 &sched_engine->lock
LOCK2 flags
HALF_LOCKED2 rcu_read
TYPE_LOCK (struct i915_sched_engine)->lock

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c intel_guc_submission_print_context_info() -> intel_context_is_parent()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
PREEMPT_ADD <- disables preempt
RX_PATH
TASK_NOT_RUNNING
LOCK2 &(&guc->context_lookup)->xa_lock
LOCK2 &m->lock
LOCK2 flags
TYPE_LOCK (struct seq_file)->lock

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c new_guc_id() -> intel_context_is_parent()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce->timeline (-1),728
BUF_SIZE 0 ce->vm (-1),1208
DATA_SOURCE 0 ce $1
STR_LEN 0 ce->engine (-1),3,6-7,11,14,17
PREEMPT_ADD
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 ce->engine->execlists.reset_ccid 0-u32max
HOST_DATA 0 ce->engine->gt->i915->uncore.fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->gt->uc.guc.mmio_msg 0
HOST_DATA 0 ce->engine->gt->uncore->fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->uncore->fifo_count 0-127,u32max
NO_OVERFLOW_SIMPLE 0 ce->ring->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->fence_size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->obj->base.size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->vm->total
NO_OVERFLOW_SIMPLE 0 ce->ring_size
NO_OVERFLOW_SIMPLE 0 ce->state->fence_size
NO_OVERFLOW_SIMPLE 0 ce->state->size
LOCK2 &guc->submission_state.lock
LOCK2 flags
HALF_LOCKED2 __flags
HALF_LOCKED2 0 ce->ring->vma->obj->base.resv
HALF_LOCKED2 0 ce->state->obj->base.resv
HALF_LOCKED2 0 ce->timeline->hwsp_ggtt->obj->base.resv
HALF_LOCKED2 0 &ce->pin_mutex
TYPE_LOCK (struct intel_guc)->submission_state.lock

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c new_guc_id() -> intel_context_is_parent()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce->timeline (-1),728
BUF_SIZE 0 ce->vm (-1),1208
DATA_SOURCE 0 ce $1
STR_LEN 0 ce->engine (-1),3,6-7,11,14,17
PREEMPT_ADD
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 ce->engine->execlists.reset_ccid 0-u32max
HOST_DATA 0 ce->engine->gt->i915->uncore.fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->gt->uc.guc.mmio_msg 0
HOST_DATA 0 ce->engine->gt->uncore->fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->uncore->fifo_count 0-127,u32max
NO_OVERFLOW_SIMPLE 0 ce->ring->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->fence_size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->obj->base.size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->vm->total
NO_OVERFLOW_SIMPLE 0 ce->ring_size
NO_OVERFLOW_SIMPLE 0 ce->state->fence_size
NO_OVERFLOW_SIMPLE 0 ce->state->size
LOCK2 &guc->submission_state.lock
LOCK2 flags
HALF_LOCKED2 __flags
HALF_LOCKED2 0 ce->ring->vma->obj->base.resv
HALF_LOCKED2 0 ce->state->obj->base.resv
HALF_LOCKED2 0 ce->timeline->hwsp_ggtt->obj->base.resv
HALF_LOCKED2 0 &ce->pin_mutex
TYPE_LOCK (struct intel_guc)->submission_state.lock

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c prepare_context_registration_info_v69() -> intel_context_is_parent()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce (-1)-s32max
DATA_SOURCE 0 ce $0
PREEMPT_ADD
RX_PATH
TASK_NOT_RUNNING

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c prepare_context_registration_info_v70() -> intel_context_is_parent()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce (-1)-s32max
DATA_SOURCE 0 ce $0
PREEMPT_ADD
RX_PATH
TASK_NOT_RUNNING

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c register_context_v69() -> intel_context_is_parent()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce (-1)-s32max
CAPPED_DATA 0 ce 1
DATA_SOURCE 0 ce $1
PREEMPT_ADD
RX_PATH
TASK_NOT_RUNNING

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c register_context_v70() -> intel_context_is_parent()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce (-1)-s32max
CAPPED_DATA 0 ce 1
DATA_SOURCE 0 ce $1
PREEMPT_ADD
RX_PATH
TASK_NOT_RUNNING

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c unpin_guc_id() -> intel_context_is_parent()

Type Parameter Key Value
PARAM_VALUE 0 ce 4096-ptr_max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce (-1)-s32max
BUF_SIZE 0 ce->timeline (-1),728
BUF_SIZE 0 ce->vm (-1)-0,1208
CAPPED_DATA 0 ce 1
DATA_SOURCE 0 ce $1
STR_LEN 0 ce->engine (-1),3,6
STR_LEN 0 ce->gem_context->i915 (-1),1,4
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 ce->engine->execlists.reset_ccid 0-u32max
HOST_DATA 0 ce->engine->gt->i915->uncore.fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->gt->uc.guc.mmio_msg 0
HOST_DATA 0 ce->engine->gt->uc.guc.timestamp.gt_stamp 0-u64max
HOST_DATA 0 ce->engine->gt->uncore->fifo_count 0-127,u32max
HOST_DATA 0 ce->engine->uncore->fifo_count 0-127,u32max
NO_OVERFLOW_SIMPLE 0 ce->ring->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->fence_size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->obj->base.size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->size
NO_OVERFLOW_SIMPLE 0 ce->ring->vma->vm->total
NO_OVERFLOW_SIMPLE 0 ce->ring_size
NO_OVERFLOW_SIMPLE 0 ce->state->fence_size
NO_OVERFLOW_SIMPLE 0 ce->state->size
HALF_LOCKED2 __flags
HALF_LOCKED2 0 &ce->pin_mutex
HALF_LOCKED2 0 &ce->timeline->mutex