Defined in 2 files as a function:
- drivers/gpu/drm/i915/display/intel_display_power.h, line 246 (as a function)
- drivers/gpu/drm/i915/display/intel_display_power.h, line 274 (as a function)
Referenced in 3 files:
- drivers/gpu/drm/i915/display/intel_display_power.h
- drivers/gpu/drm/i915/display/intel_dp_aux.c, line 462
- drivers/gpu/drm/i915/gt/intel_gt_pm.c, line 127
Smatch caller information:
drivers/gpu/drm/i915/display/intel_tc.c adlp_tc_phy_hpd_live_status() -> intel_display_power_put_async()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | display | 4096-ptr_max |
| PARAM_VALUE | 0 | display->hotplug.hpd | 4096-ptr_max |
| PARAM_VALUE | 0 | display->hotplug.pch_hpd | 4096-ptr_max |
| PARAM_VALUE | 0 | display->hotplug.poll_enabled | 0 |
| PARAM_VALUE | 0 | display->hotplug.poll_init_work.entry.next | 4096-ptr_max |
| PARAM_VALUE | 0 | display->irq.vlv_display_irqs_enabled | 1 |
| PARAM_VALUE | 0 | display->params.enable_dmc_wl | 0-1 |
| PARAM_VALUE | 0 | display->parent | 4096-ptr_max |
| PARAM_VALUE | 0 | display->power.domains.async_put_next_delay | 0 |
| PARAM_VALUE | 0 | display->power.domains.async_put_wakeref | 0 |
| PARAM_VALUE | 0 | display->power.domains.lock.osq.tail.counter | 0-s32max |
| PARAM_VALUE | 0 | display->psr_dc5_dc6_wa_work.entry.next | 4096-ptr_max |
| PARAM_VALUE | 0 | display->wl.enabled | 0 |
| PARAM_VALUE | 1 | domain | 0 |
| PARAM_VALUE | 2 | wakeref | 4096-ptr_max,(-2) |
| DATA_SOURCE | 2 | wakeref | r intel_display_power_get |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HOST_DATA | 0 | display->power.domains.dc_state | 0-u32max |
| HALF_LOCKED2 | &tc->lock |
drivers/gpu/drm/i915/display/intel_tc.c get_lane_mask() -> intel_display_power_put_async()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | display | 4096-ptr_max |
| PARAM_VALUE | 0 | display->hotplug.poll_enabled | 0 |
| PARAM_VALUE | 0 | display->hotplug.poll_init_work.entry.next | 4096-ptr_max |
| PARAM_VALUE | 0 | display->irq.vlv_display_irqs_enabled | 1 |
| PARAM_VALUE | 0 | display->params.enable_dmc_wl | 0-1 |
| PARAM_VALUE | 0 | display->parent | 4096-ptr_max |
| PARAM_VALUE | 0 | display->power.domains.async_put_next_delay | 0 |
| PARAM_VALUE | 0 | display->power.domains.async_put_wakeref | 0 |
| PARAM_VALUE | 0 | display->power.domains.lock.osq.tail.counter | 0-s32max |
| PARAM_VALUE | 0 | display->psr_dc5_dc6_wa_work.entry.next | 4096-ptr_max |
| PARAM_VALUE | 0 | display->wl.enabled | 0 |
| PARAM_VALUE | 1 | domain | 0 |
| PARAM_VALUE | 2 | wakeref | 4096-ptr_max,(-2) |
| DATA_SOURCE | 2 | wakeref | r intel_display_power_get |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HOST_DATA | 0 | display->power.domains.dc_state | 0-u32max |
| LOCK2 | &tc->lock | ||
| TYPE_LOCK | (struct intel_tc_port)->lock |
drivers/gpu/drm/i915/display/intel_tc.c get_pin_assignment() -> intel_display_power_put_async()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | display | 4096-ptr_max |
| PARAM_VALUE | 0 | display->hotplug.poll_enabled | 0 |
| PARAM_VALUE | 0 | display->hotplug.poll_init_work.entry.next | 4096-ptr_max |
| PARAM_VALUE | 0 | display->irq.vlv_display_irqs_enabled | 1 |
| PARAM_VALUE | 0 | display->params.enable_dmc_wl | 0-1 |
| PARAM_VALUE | 0 | display->parent | 4096-ptr_max |
| PARAM_VALUE | 0 | display->power.domains.async_put_next_delay | 0 |
| PARAM_VALUE | 0 | display->power.domains.async_put_wakeref | 0 |
| PARAM_VALUE | 0 | display->power.domains.lock.osq.tail.counter | 0-s32max |
| PARAM_VALUE | 0 | display->psr_dc5_dc6_wa_work.entry.next | 4096-ptr_max |
| PARAM_VALUE | 0 | display->wl.enabled | 0 |
| PARAM_VALUE | 1 | domain | 0 |
| PARAM_VALUE | 2 | wakeref | 4096-ptr_max,(-2) |
| DATA_SOURCE | 2 | wakeref | r intel_display_power_get |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HOST_DATA | 0 | display->power.domains.dc_state | 0-u32max |
| LOCK2 | &tc->lock | ||
| TYPE_LOCK | (struct intel_tc_port)->lock |
drivers/gpu/drm/i915/display/intel_tc.c icl_tc_phy_hpd_live_status() -> intel_display_power_put_async()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | display | 4096-ptr_max |
| PARAM_VALUE | 0 | display->hotplug.pch_hpd | 4096-ptr_max |
| PARAM_VALUE | 0 | display->hotplug.poll_enabled | 0 |
| PARAM_VALUE | 0 | display->hotplug.poll_init_work.entry.next | 4096-ptr_max |
| PARAM_VALUE | 0 | display->irq.vlv_display_irqs_enabled | 1 |
| PARAM_VALUE | 0 | display->params.enable_dmc_wl | 0-1 |
| PARAM_VALUE | 0 | display->parent | 4096-ptr_max |
| PARAM_VALUE | 0 | display->power.domains.async_put_next_delay | 0 |
| PARAM_VALUE | 0 | display->power.domains.async_put_wakeref | 0 |
| PARAM_VALUE | 0 | display->power.domains.lock.osq.tail.counter | 0-s32max |
| PARAM_VALUE | 0 | display->psr_dc5_dc6_wa_work.entry.next | 4096-ptr_max |
| PARAM_VALUE | 0 | display->wl.enabled | 0 |
| PARAM_VALUE | 2 | wakeref | 4096-ptr_max,(-2) |
| DATA_SOURCE | 2 | wakeref | r intel_display_power_get |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HOST_DATA | 0 | display->power.domains.dc_state | 0-u32max |
| HALF_LOCKED2 | &tc->lock |
drivers/gpu/drm/i915/display/intel_tc.c tgl_tc_phy_init() -> intel_display_power_put_async()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | display | 4096-ptr_max |
| PARAM_VALUE | 0 | display->hotplug.poll_enabled | 0 |
| PARAM_VALUE | 0 | display->hotplug.poll_init_work.entry.next | 4096-ptr_max |
| PARAM_VALUE | 0 | display->irq.vlv_display_irqs_enabled | 1 |
| PARAM_VALUE | 0 | display->params.enable_dmc_wl | 0-1 |
| PARAM_VALUE | 0 | display->parent | 4096-ptr_max |
| PARAM_VALUE | 0 | display->power.domains.async_put_next_delay | 0 |
| PARAM_VALUE | 0 | display->power.domains.async_put_wakeref | 0 |
| PARAM_VALUE | 0 | display->power.domains.lock.osq.tail.counter | 0-s32max |
| PARAM_VALUE | 0 | display->psr_dc5_dc6_wa_work.entry.next | 4096-ptr_max |
| PARAM_VALUE | 0 | display->wl.enabled | 0 |
| PARAM_VALUE | 2 | wakeref | 4096-ptr_max,(-2) |
| DATA_SOURCE | 2 | wakeref | r intel_display_power_get |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HOST_DATA | 0 | display->power.domains.dc_state | 0-u32max |
| LOCK2 | &tc->lock | ||
| TYPE_LOCK | (struct intel_tc_port)->lock |
drivers/gpu/drm/i915/display/intel_tc.c xelpdp_tc_phy_hpd_live_status() -> intel_display_power_put_async()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | display | 4096-ptr_max |
| PARAM_VALUE | 0 | display->hotplug.hpd | 4096-ptr_max |
| PARAM_VALUE | 0 | display->hotplug.pch_hpd | 4096-ptr_max |
| PARAM_VALUE | 0 | display->hotplug.poll_enabled | 0 |
| PARAM_VALUE | 0 | display->hotplug.poll_init_work.entry.next | 4096-ptr_max |
| PARAM_VALUE | 0 | display->irq.vlv_display_irqs_enabled | 1 |
| PARAM_VALUE | 0 | display->params.enable_dmc_wl | 0-1 |
| PARAM_VALUE | 0 | display->parent | 4096-ptr_max |
| PARAM_VALUE | 0 | display->power.domains.async_put_next_delay | 0 |
| PARAM_VALUE | 0 | display->power.domains.async_put_wakeref | 0 |
| PARAM_VALUE | 0 | display->power.domains.lock.osq.tail.counter | 0-s32max |
| PARAM_VALUE | 0 | display->psr_dc5_dc6_wa_work.entry.next | 4096-ptr_max |
| PARAM_VALUE | 0 | display->wl.enabled | 0 |
| PARAM_VALUE | 1 | domain | 0 |
| PARAM_VALUE | 2 | wakeref | 4096-ptr_max,(-2) |
| DATA_SOURCE | 2 | wakeref | r intel_display_power_get |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HOST_DATA | 0 | display->power.domains.dc_state | 0-u32max |
| HALF_LOCKED2 | &tc->lock |
drivers/gpu/drm/i915/display/intel_dp.c intel_digital_port_connected_locked() -> intel_display_power_put_async()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | display | 4096-ptr_max |
| PARAM_VALUE | 0 | display->hotplug.poll_enabled | 0 |
| PARAM_VALUE | 0 | display->hotplug.poll_init_work.entry.next | 4096-ptr_max |
| PARAM_VALUE | 0 | display->irq.vlv_display_irqs_enabled | 1 |
| PARAM_VALUE | 0 | display->parent | 4096-ptr_max |
| PARAM_VALUE | 0 | display->power.domains.async_put_next_delay | 0 |
| PARAM_VALUE | 0 | display->power.domains.async_put_wakeref | 0 |
| PARAM_VALUE | 0 | display->power.domains.lock.osq.tail.counter | 0-s32max |
| PARAM_VALUE | 0 | display->psr_dc5_dc6_wa_work.entry.next | 4096-ptr_max |
| PARAM_VALUE | 0 | display->wl.enabled | 0 |
| PARAM_VALUE | 1 | domain | 0 |
| PARAM_VALUE | 2 | wakeref | 4096-ptr_max,(-2) |
| DATA_SOURCE | 2 | wakeref | r intel_display_power_get |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HOST_DATA | 0 | display->power.domains.dc_state | 0-u32max |
drivers/gpu/drm/i915/gt/intel_gt_pm.c __gt_park() -> intel_display_power_put_async()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 1 | domain | 72 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| LOCK2 | &wf->mutex | ||
| TYPE_LOCK | (struct intel_wakeref)->mutex |
drivers/gpu/drm/i915/display/intel_cmtg.c intel_cmtg_transcoder_is_secondary() -> intel_display_power_put_async()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | display | 4096-ptr_max |
| PARAM_VALUE | 0 | display->drm | 4096-ptr_max |
| PARAM_VALUE | 0 | display->hotplug.poll_init_work.entry.next | 4096-ptr_max |
| PARAM_VALUE | 0 | display->info.__device_info | 4096-ptr_max |
| PARAM_VALUE | 0 | display->params.enable_dmc_wl | 0-1 |
| PARAM_VALUE | 0 | display->parent | 4096-ptr_max |
| PARAM_VALUE | 0 | display->pmdemand.lock.osq.tail.counter | 0-s32max |
| PARAM_VALUE | 0 | display->power.domains.async_put_next_delay | 0 |
| PARAM_VALUE | 0 | display->power.domains.async_put_wakeref | 0 |
| PARAM_VALUE | 0 | display->power.domains.initializing | 1 |
| PARAM_VALUE | 0 | display->power.domains.lock.osq.tail.counter | 0-s32max |
| PARAM_VALUE | 0 | display->psr_dc5_dc6_wa_work.entry.next | 4096-ptr_max |
| PARAM_VALUE | 0 | display->wm.g4x.hpll.cursor | 0-63 |
| PARAM_VALUE | 0 | display->wm.g4x.hpll.fbc | 0-15 |
| PARAM_VALUE | 0 | display->wm.g4x.hpll.plane | 0-511 |
| PARAM_VALUE | 0 | display->wm.g4x.sr.cursor | 0-63 |
| PARAM_VALUE | 0 | display->wm.g4x.sr.fbc | 0-7 |
| PARAM_VALUE | 0 | display->wm.g4x.sr.plane | 0-511 |
| PARAM_VALUE | 0 | display->wm.hw.partitioning | 0-1 |
| PARAM_VALUE | 0 | display->wm.vlv.level | 0-2 |
| PARAM_VALUE | 0 | display->wm.vlv.sr.cursor | 0-63 |
| PARAM_VALUE | 0 | display->wm.vlv.sr.plane | 0-2047 |
| PARAM_VALUE | 1 | domain | 9-10 |
| PARAM_VALUE | 2 | wakeref | 4096-ptr_max,(-2) |
| CAPPED_DATA | 0 | display->dpll.num_dpll | 1 |
| DATA_SOURCE | 0 | display | $0 |
| DATA_SOURCE | 2 | wakeref | r intel_display_power_get_if_enabled |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HOST_DATA | 0 | display->cdclk.hw.cdclk | 0-16[c] |
| HOST_DATA | 0 | display->cdclk.hw.joined_mbus | 0-1 |
| HOST_DATA | 0 | display->cdclk.hw.voltage_level | 0-31[c] |
| HOST_DATA | 0 | display->cdclk.max_cdclk_freq | 1-39168016[c] |
| HOST_DATA | 0 | display->fdi.pll_freq | 20000-2570000[c] |
| HOST_DATA | 0 | display->fdi.rx_config | 0,32768-98304[c] |
| HOST_DATA | 0 | display->power.domains.dc_state | 0-u32max |
| HOST_DATA | 0 | display->state.bxt_phy_grc | 0-u32max |
| HOST_DATA | 0 | display->wm.g4x.cxsr | 0-1 |
| HOST_DATA | 0 | display->wm.g4x.hpll.cursor | 0-63[c] |
| HOST_DATA | 0 | display->wm.g4x.hpll.fbc | 0-15[c] |
| HOST_DATA | 0 | display->wm.g4x.hpll.plane | 0-511[c] |
| HOST_DATA | 0 | display->wm.g4x.sr.cursor | 0-63[c] |
| HOST_DATA | 0 | display->wm.g4x.sr.fbc | 0-7[c] |
| HOST_DATA | 0 | display->wm.g4x.sr.plane | 0-511 |
| HOST_DATA | 0 | display->wm.vlv.cxsr | 0-1 |
| HOST_DATA | 0 | display->wm.vlv.sr.cursor | 0-63[c] |
| HOST_DATA | 0 | display->wm.vlv.sr.plane | 0-2047[c] |
| HALF_LOCKED2 | &display->drm->mode_config.connection_mutex | ||
| HALF_LOCKED2 | &display->drm->mode_config.mutex |
drivers/gpu/drm/i915/display/intel_display.c enabled_bigjoiner_pipes() -> intel_display_power_put_async()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | display | 4096-ptr_max |
| PARAM_VALUE | 0 | display->params.enable_dmc_wl | 0-1 |
| PARAM_VALUE | 0 | display->parent | 4096-ptr_max |
| PARAM_VALUE | 0 | display->power.domains.async_put_next_delay | 0 |
| PARAM_VALUE | 0 | display->power.domains.async_put_wakeref | 0 |
| PARAM_VALUE | 0 | display->power.domains.lock.osq.tail.counter | 0-s32max |
| PARAM_VALUE | 2 | wakeref | 4096-ptr_max,(-2) |
| CAPPED_DATA | 0 | &display->pipe_list | 1 |
| DATA_SOURCE | 0 | display | $0 |
| DATA_SOURCE | 1 | domain | r intel_dsc_power_domain |
| DATA_SOURCE | 2 | wakeref | r intel_display_power_get_if_enabled |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HOST_DATA | 0 | display->power.domains.dc_state | 0-u32max |
| HOST_DATA | 0 | display->state.bxt_phy_grc | 0-u32max |
drivers/gpu/drm/i915/display/intel_display.c enabled_ultrajoiner_pipes() -> intel_display_power_put_async()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | display | 4096-ptr_max |
| PARAM_VALUE | 0 | display->params.enable_dmc_wl | 0-1 |
| PARAM_VALUE | 0 | display->parent | 4096-ptr_max |
| PARAM_VALUE | 0 | display->platform.dgfx | 1 |
| PARAM_VALUE | 0 | display->power.domains.async_put_next_delay | 0 |
| PARAM_VALUE | 0 | display->power.domains.async_put_wakeref | 0 |
| PARAM_VALUE | 0 | display->power.domains.lock.osq.tail.counter | 0-s32max |
| PARAM_VALUE | 2 | wakeref | 4096-ptr_max,(-2) |
| CAPPED_DATA | 0 | &display->pipe_list | 1 |
| DATA_SOURCE | 0 | display | $0 |
| DATA_SOURCE | 1 | domain | r intel_dsc_power_domain |
| DATA_SOURCE | 2 | wakeref | r intel_display_power_get_if_enabled |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HOST_DATA | 0 | display->power.domains.dc_state | 0-u32max |
| HOST_DATA | 0 | display->state.bxt_phy_grc | 0-u32max |
drivers/gpu/drm/i915/display/intel_display.c enabled_uncompressed_joiner_pipes() -> intel_display_power_put_async()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | display | 4096-ptr_max |
| PARAM_VALUE | 0 | display->params.enable_dmc_wl | 0-1 |
| PARAM_VALUE | 0 | display->parent | 4096-ptr_max |
| PARAM_VALUE | 0 | display->power.domains.async_put_next_delay | 0 |
| PARAM_VALUE | 0 | display->power.domains.async_put_wakeref | 0 |
| PARAM_VALUE | 0 | display->power.domains.lock.osq.tail.counter | 0-s32max |
| PARAM_VALUE | 2 | wakeref | 4096-ptr_max,(-2) |
| CAPPED_DATA | 0 | &display->pipe_list | 1 |
| DATA_SOURCE | 0 | display | $0 |
| DATA_SOURCE | 2 | wakeref | r intel_display_power_get_if_enabled |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HOST_DATA | 0 | display->power.domains.dc_state | 0-u32max |
| HOST_DATA | 0 | display->state.bxt_phy_grc | 0-u32max |
drivers/gpu/drm/i915/display/intel_display.c hsw_enabled_transcoders() -> intel_display_power_put_async()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | display | 4096-ptr_max |
| PARAM_VALUE | 0 | display->info.__device_info | 4096-ptr_max |
| PARAM_VALUE | 0 | display->params.enable_dmc_wl | 0-1 |
| PARAM_VALUE | 0 | display->parent | 4096-ptr_max |
| PARAM_VALUE | 0 | display->power.domains.async_put_next_delay | 0 |
| PARAM_VALUE | 0 | display->power.domains.async_put_wakeref | 0 |
| PARAM_VALUE | 0 | display->power.domains.lock.osq.tail.counter | 0-s32max |
| PARAM_VALUE | 1 | domain | 9-15 |
| PARAM_VALUE | 2 | wakeref | 4096-ptr_max,(-2) |
| DATA_SOURCE | 2 | wakeref | r intel_display_power_get_if_enabled |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HOST_DATA | 0 | display->power.domains.dc_state | 0-u32max |
drivers/gpu/drm/i915/display/intel_display.c transcoder_ddi_func_is_enabled() -> intel_display_power_put_async()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | display | 4096-ptr_max |
| PARAM_VALUE | 0 | display->hotplug.poll_enabled | 0 |
| PARAM_VALUE | 0 | display->info.__device_info | 4096-ptr_max |
| PARAM_VALUE | 0 | display->irq.vlv_display_irqs_enabled | 1 |
| PARAM_VALUE | 0 | display->params.enable_dmc_wl | 0-1 |
| PARAM_VALUE | 0 | display->parent | 4096-ptr_max |
| PARAM_VALUE | 0 | display->power.domains.async_put_next_delay | 0 |
| PARAM_VALUE | 0 | display->power.domains.async_put_wakeref | 0 |
| PARAM_VALUE | 0 | display->power.domains.lock.osq.tail.counter | 0-s32max |
| PARAM_VALUE | 0 | display->psr_dc5_dc6_wa_work.entry.next | 4096-ptr_max |
| PARAM_VALUE | 0 | display->wl.enabled | 0 |
| PARAM_VALUE | 1 | domain | 0-13,2147483657-u32max |
| PARAM_VALUE | 2 | wakeref | 4096-ptr_max,(-2) |
| DATA_SOURCE | 0 | display | $0 |
| DATA_SOURCE | 2 | wakeref | r intel_display_power_get_if_enabled |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HOST_DATA | 0 | display->power.domains.dc_state | 0-u32max |
| HOST_DATA | 0 | display->state.bxt_phy_grc | 0-u32max |
drivers/gpu/drm/i915/display/intel_dp_aux.c intel_dp_aux_xfer() -> intel_display_power_put_async()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | display | 4096-ptr_max |
| PARAM_VALUE | 0 | display->dkl.phy_lock.rlock.dep_map->name | 0-255 |
| PARAM_VALUE | 0 | display->dmc.dmc->dc6_allowed.count | 0-4294967295 |
| PARAM_VALUE | 0 | display->dmc.dmc->dc6_allowed.dc5_start | 0-4294967295 |
| PARAM_VALUE | 0 | display->hotplug.poll_enabled | 0 |
| PARAM_VALUE | 0 | display->hotplug.poll_init_work.entry.next | 4096-ptr_max |
| PARAM_VALUE | 0 | display->hotplug.poll_init_work.entry.next->prev | 4096-ptr_max |
| PARAM_VALUE | 0 | display->irq.vlv_display_irqs_enabled | 1 |
| PARAM_VALUE | 0 | display->parent | 4096-ptr_max |
| PARAM_VALUE | 0 | display->power.domains.async_put_next_delay | 0 |
| PARAM_VALUE | 0 | display->power.domains.async_put_wakeref | 0 |
| PARAM_VALUE | 0 | display->power.domains.async_put_work.work.entry.next->prev | 4096-ptr_max |
| PARAM_VALUE | 0 | display->power.domains.lock.dep_map->name | 0-255 |
| PARAM_VALUE | 0 | display->power.domains.lock.first_waiter->list.prev->next | 5159360019465732096 |
| PARAM_VALUE | 0 | display->power.domains.lock.first_waiter->task->blocked_lock.dep_map->name | 0-255 |
| PARAM_VALUE | 0 | display->power.domains.lock.first_waiter->task->blocked_lock.owner | (-1) |
| PARAM_VALUE | 0 | display->power.domains.lock.first_waiter->task->blocked_lock.owner_cpu | 4294967295 |
| PARAM_VALUE | 0 | display->power.domains.lock.first_waiter->task->blocked_lock.raw_lock.val.counter | s32min-s32max |
| PARAM_VALUE | 0 | display->power.domains.lock.first_waiter->task->usage.refs.counter | s32min-s32max |
| PARAM_VALUE | 0 | display->power.domains.lock.osq.tail.counter | 0-s32max |
| PARAM_VALUE | 0 | display->power.domains.power_wells->count | s32min-s32max |
| PARAM_VALUE | 0 | display->power.domains.power_wells->hw_enabled | 1 |
| PARAM_VALUE | 0 | display->psr_dc5_dc6_wa_work.entry.next | 4096-ptr_max |
| PARAM_VALUE | 0 | display->wl.enabled | 0 |
| PARAM_VALUE | 0 | display->wl.work.work.entry.next->next | 1-u64max |
| PARAM_VALUE | 0 | display->wl.work.work.entry.next->prev | 4096-ptr_max |
| PARAM_VALUE | 0 | display->wl.work.work.entry.prev->next | 1-u64max |
| PARAM_VALUE | 0 | display->wl.work.work.entry.prev->prev | 1-u64max |
| PARAM_VALUE | 0 | *display->irq.pipestat_irq_mask | 0-4294967295 |
| PARAM_VALUE | 2 | wakeref | 4096-ptr_max,(-2) |
| DATA_SOURCE | 1 | domain | r intel_aux_power_domain |
| DATA_SOURCE | 2 | wakeref | r intel_display_power_get |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HOST_DATA | 0 | display->dmc.dmc->dc6_allowed.dc5_start | 0-4294967295 |
| HOST_DATA | 0 | display->power.domains.dc_state | 0-u32max |
| HALF_LOCKED2 | &aux->hw_mutex | ||
| HALF_LOCKED2 | &display->pps.mutex |