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Defined in 1 files as a prototype:

Defined in 1 files as a function:

Referenced in 2 files:

Smatch caller information:

drivers/gpu/drm/i915/display/intel_cdclk.c bxt_set_cdclk() -> intel_parent_pcode_write_timeout()

Type Parameter Key Value
PARAM_VALUE 0 display 4096-ptr_max
PARAM_VALUE 0 display->cdclk.funcs 4096-ptr_max
PARAM_VALUE 0 display->cdclk.funcs->set_cdclk 0,981987470656221184,2279366636571783168,7605838049097428992,7713557352659574784,8715991085883871232
PARAM_VALUE 0 display->drm 0,4096-ptr_max
PARAM_VALUE 0 display->parent->vlv_iosf 0,197119610173992960
PARAM_VALUE 0 display->platform.dg2 0
PARAM_VALUE 0 display->wl.work.work.entry.next->next 1-u64max
PARAM_VALUE 0 display->wl.work.work.entry.prev->next 1-u64max
PARAM_VALUE 0 display->wl.work.work.entry.prev->prev 1-u64max
PARAM_VALUE 0 *display->irq.pipestat_irq_mask 0-4294967295
PARAM_VALUE 1 mbox 23
PARAM_VALUE 2 val 2147483648
PARAM_VALUE 3 timeout_ms 2
BUF_SIZE 0 display (-1),8128
BUF_SIZE 0 display (-1),8128
DATA_SOURCE 0 display $0
STR_LEN 0 display (-1),21-22
STR_LEN 0 display (-1),21-22
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 display->cdclk.hw.joined_mbus 0-1
HOST_DATA 0 display->drm->mode_config.object_idr.idr_rt.xa_flags 0-u32max
HOST_DATA 0 display->power.chv_phy_control 0-u32max[c]
HOST_DATA 0 display->power.domains.dc_state 0-u32max
HOST_DATA 0 display->state.bxt_phy_grc 0-u32max
NO_OVERFLOW_SIMPLE 0 display->drm->num_crtcs
HALF_LOCKED2 0 &display->gmbus.mutex

drivers/gpu/drm/i915/display/intel_cdclk.c bxt_set_cdclk() -> intel_parent_pcode_write_timeout()

Type Parameter Key Value
PARAM_VALUE 0 display 4096-ptr_max
PARAM_VALUE 0 display->cdclk.funcs 4096-ptr_max
PARAM_VALUE 0 display->cdclk.funcs->set_cdclk 0,981987470656221184,2279366636571783168,7605838049097428992,7713557352659574784,8715991085883871232
PARAM_VALUE 0 display->cdclk.table->waveform 0,34952,37448,42148,42314,43604,43690,44378,46774,56246,61166,63454,65278,65534-u16max
PARAM_VALUE 0 display->drm 0,4096-ptr_max
PARAM_VALUE 0 display->drm->huge_mnt->mnt_sb->s_cop->inode_info_offs 1632,1720,2632,2648
PARAM_VALUE 0 display->info.__device_info 4096-ptr_max
PARAM_VALUE 0 display->params.enable_dmc_wl 0-1
PARAM_VALUE 0 display->parent 4096-ptr_max
PARAM_VALUE 0 display->parent->pcode 4096-ptr_max
PARAM_VALUE 0 display->parent->pcode->write 4096-ptr_max
PARAM_VALUE 0 display->parent->vlv_iosf 0,197119610173992960
PARAM_VALUE 0 display->wl.work.timer.entry->pprev 4096-ptr_max
PARAM_VALUE 0 display->wl.work.work.entry.next->next 1-u64max
PARAM_VALUE 0 display->wl.work.work.entry.prev->next 1-u64max
PARAM_VALUE 0 display->wl.work.work.entry.prev->prev 1-u64max
PARAM_VALUE 0 *display->irq.pipestat_irq_mask 0-4294967295
PARAM_VALUE 1 mbox 23
PARAM_VALUE 3 timeout_ms 2
BUF_SIZE 0 display (-1),8128
BUF_SIZE 0 display (-1),8128
DATA_SOURCE 0 display $0
STR_LEN 0 display (-1),21-22
STR_LEN 0 display (-1),21-22
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 display->cdclk.hw.joined_mbus 0-1
HOST_DATA 0 display->drm->mode_config.object_idr.idr_rt.xa_flags 0-u32max
HOST_DATA 0 display->power.chv_phy_control 0-u32max[c]
HOST_DATA 0 display->power.domains.dc_state 0-u32max
HOST_DATA 0 display->state.bxt_phy_grc 0-u32max
NO_OVERFLOW_SIMPLE 0 display->drm->num_crtcs
HALF_LOCKED2 0 &display->gmbus.mutex

drivers/gpu/drm/i915/display/intel_parent.c intel_parent_pcode_write() -> intel_parent_pcode_write_timeout()

Type Parameter Key Value
PARAM_VALUE 0 display 4096-ptr_max
PARAM_VALUE 0 display->cdclk.funcs->set_cdclk 0,981987470656221184,2279366636571783168,7605838049097428992,7713557352659574784,8715991085883871232
PARAM_VALUE 0 display->cdclk.table->cdclk 0,79200,144000,151200,153600,158400,163200,172800,176000,176400,179200,180000,192000,201600,204000,211200,226800,230400,244800,249600,252000,268800,277200,285600,288000,302400,307200,312000,316800,324000,326400-4294967295
PARAM_VALUE 0 display->cdclk.table->ratio 0,9-10,14-41,46,50,52,54,58,60,64-65,68,92,108,116,136
PARAM_VALUE 0 display->cdclk.table->refclk 0,19200,24000,24400,38400
PARAM_VALUE 0 display->cdclk.table->waveform 0,6,34952,37448,42148,42314,43604,43690,44378,46774,56246,61166,63454,65278,65534-u16max
PARAM_VALUE 0 display->dpll.mgr->compare_hw_state 1988828769907408896,4304445909437353984,5589390013801357312,7199724579178258432,7292826417019408384,7481167222828003328,8665324935750119424,9182544845536616448
PARAM_VALUE 0 display->dpll.mgr->compute_dplls 3278772287333720064,5266472627050582016,6060912680081088512,6216086186862542848,8471094383317381120,8614942105147809792,8986272695562289152,9022440569105731584
PARAM_VALUE 0 display->dpll.mgr->dump_hw_state 90682934213672960,215385455013437440,1582718613836124160,1835901918492803072,4180342879337267200,5224410778052669440,6129327221765451776,9060799253560999936
PARAM_VALUE 0 display->dpll.mgr->get_dplls 204657350407954432,3936139357776248832,4663370074112573440,5334416601241935872,6868165492758421504,8361789056745369600,8976139343680507904
PARAM_VALUE 0 display->dpll.mgr->put_dplls 1769282744316076032,3032660624085295104
PARAM_VALUE 0 display->dpll.mgr->update_active_dpll 0,3893979238484942848
PARAM_VALUE 0 display->dpll.mgr->update_ref_clks 0,3536181015747457024,6167602680813006848,6325637718150250496,6483930178044678144
PARAM_VALUE 0 display->drm->mode_config.helper_private->atomic_commit_tail 0,113,234517204248432640,264416658693812224,1002985563129995264,1135616218159751168,1435312838172803072,1559742614509715456,1682444203744997376,2792895115794366464,3649211429048074240,4264110321136541696,4348468181405868032-s64max
PARAM_VALUE 0 display->parent->irq 5062596649199198208
PARAM_VALUE 0 display->parent->pcode 4096-ptr_max
PARAM_VALUE 0 display->parent->pcode->request 4096-ptr_max
PARAM_VALUE 0 display->parent->pcode->write 4096-ptr_max
PARAM_VALUE 0 display->parent->rpm 1303590034781167616
PARAM_VALUE 0 display->parent->vlv_iosf 197119610173992960
PARAM_VALUE 0 display->restore.reset_ctx.ww_ctx.ww_class->is_wait_die 0-1
PARAM_VALUE 0 display->wm.funcs->atomic_update_watermarks 0,241866399159836672
PARAM_VALUE 0 display->wm.funcs->compute_global_watermarks 0,7679025112587603968
PARAM_VALUE 0 display->wm.funcs->compute_watermarks 0,663047380929499136,4718310602505961472,7447224825039265792,8278299763477639168
PARAM_VALUE 0 display->wm.funcs->get_hw_state 0,1372658440782848000,6903309568198033408,7899623770445606912,8633453788894511104
PARAM_VALUE 0 display->wm.funcs->initial_watermarks 0,318382624811003904,2077638626766659584,4361408001915691008
PARAM_VALUE 0 display->wm.funcs->optimize_watermarks 0,136016925988110336,2676780419539894272,6733336501198520320
PARAM_VALUE 0 display->wm.funcs->sanitize 0,3771904337417297920,8756858967241641984,9118998679592730624
PARAM_VALUE 0 display->wm.funcs->update_wm 0,2900677620984037376,5075417898438156288,6224038869724659712,6233422041516032000
PARAM_VALUE 0 *display->irq.pipestat_irq_mask 0-4294967295
PARAM_VALUE 1 mbox 5,7,17-18,23-25,33
PARAM_VALUE 3 timeout_ms 1
BUF_SIZE 0 display->hotplug.dp_wq (-1),512,528-8720
BUF_SIZE 0 display->wq.cleanup (-1),512,528-8720
BUF_SIZE 0 display->wq.flip (-1),512,528-8720
BUF_SIZE 0 display->wq.modeset (-1),512,528-8720
BUF_SIZE 0 display->wq.unordered (-1),512,528-8720
DATA_SOURCE 0 display $0
DATA_SOURCE 1 mbox $1
DATA_SOURCE 2 val $2
STR_LEN 0 display (-1),21-22
STR_LEN 0 display (-1),21-22
HARD_MAX 1 mbox 33
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 display->cdclk.hw.cdclk 0-39168016[c]
HOST_DATA 0 display->cdclk.hw.joined_mbus 0-1
HOST_DATA 0 display->cdclk.hw.voltage_level 0-31[c]
HOST_DATA 0 display->cdclk.max_cdclk_freq 1-39168016[c]
HOST_DATA 0 display->drm->mode_config.connector_ida.xa.xa_flags 67108869
HOST_DATA 0 display->drm->mode_config.object_idr.idr_rt.xa_flags 0,4-u32max
HOST_DATA 0 display->drm->mode_config.tile_idr.idr_rt.xa_flags 0,67108864-u32max
HOST_DATA 0 display->drm->num_crtcs 2[c]
HOST_DATA 0 display->fdi.rx_config 0,32768-98304[c]
HOST_DATA 0 display->power.chv_phy_control 0-u32max[c]
HOST_DATA 0 display->power.domains.dc_state 0-u32max
HOST_DATA 0 display->restore.saveGCDGMBUS 0-u16max
HOST_DATA 0 display->state.bxt_phy_grc 0-u32max
HOST_DATA 0 display->wm.g4x.cxsr 0-1
HOST_DATA 0 display->wm.g4x.hpll.cursor 0-63[c]
HOST_DATA 0 display->wm.g4x.hpll.fbc 0-15[c]
HOST_DATA 0 display->wm.g4x.hpll.plane 0-511[c]
HOST_DATA 0 display->wm.g4x.sr.cursor 0-63[c]
HOST_DATA 0 display->wm.g4x.sr.fbc 0-7[c]
HOST_DATA 0 display->wm.g4x.sr.plane 0-511
HOST_DATA 0 display->wm.vlv.cxsr 0-1
HOST_DATA 0 display->wm.vlv.sr.cursor 0-63[c]
HOST_DATA 0 display->wm.vlv.sr.plane 0-2047[c]
HOST_DATA 2 val 0-u32max
NO_OVERFLOW_SIMPLE 0 display->drm->mode_config.num_colorop
NO_OVERFLOW_SIMPLE 0 display->drm->mode_config.num_crtc
NO_OVERFLOW_SIMPLE 0 display->drm->mode_config.num_total_plane
NO_OVERFLOW_SIMPLE 0 display->drm->num_crtcs
NO_OVERFLOW_SIMPLE 0 display->hotplug.dp_wq->rescuer->task->dl.dl_runtime
NO_OVERFLOW_SIMPLE 0 display->restore.modeset_state->num_connector
NO_OVERFLOW_SIMPLE 0 display->wq.cleanup->rescuer->task->dl.dl_runtime
NO_OVERFLOW_SIMPLE 0 display->wq.flip->rescuer->task->dl.dl_runtime
NO_OVERFLOW_SIMPLE 0 display->wq.modeset->rescuer->task->dl.dl_runtime
NO_OVERFLOW_SIMPLE 0 display->wq.unordered->rescuer->task->dl.dl_runtime
HALF_LOCKED2 &dig_port->hdcp.mutex
HALF_LOCKED2 &hdcp->mutex
HALF_LOCKED2 &power_domains->lock
HALF_LOCKED2 0 &display->dpll.lock
HALF_LOCKED2 0 &display->drm->mode_config.connection_mutex
HALF_LOCKED2 0 &display->drm->mode_config.mutex
HALF_LOCKED2 0 &display->gmbus.mutex