| PARAM_VALUE |
0 |
phba |
4096-ptr_max |
| BUF_SIZE |
0 |
phba |
(-1),64,128,280,1024 |
| BUF_SIZE |
0 |
phba |
(-1),64,128,280,1024 |
| DATA_SOURCE |
0 |
phba |
$0 |
| RX_PATH |
|
|
|
| TASK_NOT_RUNNING |
|
|
|
| HOST_DATA |
0 |
phba->pcb->hgpAddrHigh |
0[c] |
| HOST_DATA |
0 |
phba->pcidev->current_state |
0-3[c] |
| HOST_DATA |
0 |
phba->sli4_hba->asic_rev |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba->conf_trunk |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba->cq_ecount |
s32min-s32max |
| HOST_DATA |
0 |
phba->sli4_hba->cq_esize |
s32min-s32max |
| HOST_DATA |
0 |
phba->sli4_hba->cq_max |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba->curr_disp_cpu |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba->els_xri_cnt |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba->encryption_support |
0-1 |
| HOST_DATA |
0 |
phba->sli4_hba->eq_ecount |
s32min-s32max |
| HOST_DATA |
0 |
phba->sli4_hba->eq_esize |
s32min-s32max |
| HOST_DATA |
0 |
phba->sli4_hba->extents_in_use |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba->fawwpn_flag |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba->flash_id |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba->fw_func_mode |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba->intr_enable |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba->io_xri_cnt |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba->io_xri_max |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba->io_xri_start |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba->mq_ecount |
s32min-s32max |
| HOST_DATA |
0 |
phba->sli4_hba->mq_esize |
s32min-s32max |
| HOST_DATA |
0 |
phba->sli4_hba->next_rpi |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba->next_xri |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba->num_possible_cpu |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba->num_present_cpu |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba->nvmet_io_wait_cnt |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba->nvmet_io_wait_total |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba->nvmet_xri_cnt |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba->oas_next_lun |
0-u64max |
| HOST_DATA |
0 |
phba->sli4_hba->physical_port |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba->pport_name_sta |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba->rpi_count |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba->rpi_hdrs_in_use |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba->rq_ecount |
s32min-s32max |
| HOST_DATA |
0 |
phba->sli4_hba->rq_esize |
s32min-s32max |
| HOST_DATA |
0 |
phba->sli4_hba->ue_mask_hi |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba->ue_mask_lo |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba->ue_to_rp |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba->ue_to_sr |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba->vfi_count |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba->wq_ecount |
s32min-s32max |
| HOST_DATA |
0 |
phba->sli4_hba->wq_esize |
s32min-s32max |
| HOST_DATA |
0 |
phba->sli4_hba.asic_id.word0 |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.bbscn_params.word0 |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.bmbx.aphys |
0-u64max |
| HOST_DATA |
0 |
phba->sli4_hba.bmbx.bmbx_size |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.bmbx.dma_address.addr_hi |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.bmbx.dma_address.addr_lo |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.iov.pf_number |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.iov.vf_number |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.link_state.duplex |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba.link_state.fault |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba.link_state.link_status |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba.link_state.logical_speed |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.link_state.number |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba.link_state.speed |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.link_state.status |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba.link_state.topology |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba.link_state.type |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba.lnk_info.lnk_dv |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba.lnk_info.lnk_no |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba.lnk_info.lnk_tp |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba.lnk_info.optic_state |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba.max_cfg_param.fcfi_used |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba.max_cfg_param.max_cq |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba.max_cfg_param.max_eq |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba.max_cfg_param.max_fcfi |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba.max_cfg_param.max_rpi |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba.max_cfg_param.max_rq |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba.max_cfg_param.max_vfi |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba.max_cfg_param.max_vpi |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba.max_cfg_param.max_wq |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba.max_cfg_param.max_xri |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba.max_cfg_param.rpi_base |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba.max_cfg_param.rpi_used |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba.max_cfg_param.vfi_base |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba.max_cfg_param.vfi_used |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba.max_cfg_param.vpi_base |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba.max_cfg_param.vpi_used |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba.max_cfg_param.xri_base |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba.max_cfg_param.xri_used |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.bv1s |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.cmf |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.cq_pages_max |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.cqav |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.cqe_size |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.cqv |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.eq_pages_max |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.eqav |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.eqe_size |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.featurelevel_1 |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.featurelevel_2 |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.hdr_pages_max |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.hdr_pp_align |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.hdr_size |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.if_page_sz |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.if_type |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.loopbk_scope |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.mi_cap |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.mi_value |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.mi_ver |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.mib_bde_cnt |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.mib_size |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.mq_elem_cnt |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.mq_pages_max |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.mqe_size |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.mqv |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.nvme |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.oas_supported |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.pls |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.proto_types |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.rq_db_window |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.rq_pages_max |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.rqe_size |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.rqv |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.sge_supp_len |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.sgl_pages_max |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.sgl_pp_align |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.sli_family |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.sli_rev |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.supported |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.wq_pages_max |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.wqe_size |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.wqpcnt |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.wqsize |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba.pc_sli4_params.wqv |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba.sli4_flags.word0 |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.sli_intf.word0 |
0-u32max |
| HOST_DATA |
0 |
phba->sli4_hba.wwnn.u.name |
0-u64max |
| HOST_DATA |
0 |
phba->sli4_hba.wwnn.u.s.IEEEextLsb |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba.wwnn.u.s.IEEEextMsn |
0-15 |
| HOST_DATA |
0 |
phba->sli4_hba.wwnn.u.s.nameType |
0-15 |
| HOST_DATA |
0 |
phba->sli4_hba.wwnn.u.wwn_be |
0-u64max |
| HOST_DATA |
0 |
phba->sli4_hba.wwpn.u.name |
0-u64max |
| HOST_DATA |
0 |
phba->sli4_hba.wwpn.u.s.IEEEextLsb |
0-255 |
| HOST_DATA |
0 |
phba->sli4_hba.wwpn.u.s.IEEEextMsn |
0-15 |
| HOST_DATA |
0 |
phba->sli4_hba.wwpn.u.s.nameType |
0-15 |
| HOST_DATA |
0 |
phba->sli4_hba.wwpn.u.wwn_be |
0-u64max |
| NO_OVERFLOW_SIMPLE |
0 |
phba->ModelDesc |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->ModelName |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->cfg_irq_chann |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->device_data_mem_pool->min_nr |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->lpfc_cmd_rsp_buf_pool->allocation |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->lpfc_cmd_rsp_buf_pool->dev->cma_area->available_count |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->lpfc_drb_pool->allocation |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->lpfc_hbq_pool->allocation |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->lpfc_hbq_pool->dev->cma_area->available_count |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->lpfc_hrb_pool->allocation |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->lpfc_mbuf_pool->allocation |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->lpfc_mbuf_pool->dev->cma_area->available_count |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->lpfc_sg_dma_buf_pool->allocation |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->lpfc_sg_dma_buf_pool->dev->cma_area->available_count |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->mbox_mem_pool->min_nr |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->nlp_mem_pool->min_nr |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->pcidev->dev.cma_area->available_count |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->pcidev->msix_base |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->pport->phba->pcidev->dev.cma_area->available_count |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->rrq_pool->min_nr |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.dat_rq |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.dat_rq->page_size |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.dat_rq->phba->pcidev->dev.cma_area->available_count |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.dat_rq->rqbp |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.els_cq |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.els_cq->page_size |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.els_cq->phba->pcidev->dev.cma_area->available_count |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.els_cq->rqbp |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.els_wq |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.els_wq->page_size |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.els_wq->phba->pcidev->dev.cma_area->available_count |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.els_wq->rqbp |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.hdr_rq |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.hdr_rq->page_size |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.hdr_rq->phba->pcidev->dev.cma_area->available_count |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.hdr_rq->rqbp |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.mbx_cq |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.mbx_cq->page_size |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.mbx_cq->phba->pcidev->dev.cma_area->available_count |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.mbx_cq->rqbp |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.mbx_wq |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.mbx_wq->page_size |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.mbx_wq->phba->pcidev->dev.cma_area->available_count |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.mbx_wq->rqbp |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.num_possible_cpu |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.nvmels_cq |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.nvmels_cq->page_size |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.nvmels_cq->phba->pcidev->dev.cma_area->available_count |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.nvmels_cq->rqbp |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.nvmels_wq |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.nvmels_wq->page_size |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.nvmels_wq->phba->pcidev->dev.cma_area->available_count |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.nvmels_wq->rqbp |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.nvmet_cqset |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.nvmet_ctx_info |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.nvmet_mrq_data |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->sli4_hba.nvmet_mrq_hdr |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->vpi_bmask |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->worker_thread->dl.dl_runtime |
|
| NO_OVERFLOW_SIMPLE |
0 |
phba->worker_thread->dl.pi_se->dl_runtime |
|
| HALF_LOCKED2 |
0 |
&phba->epd_pool.lock |
|
| HALF_LOCKED2 |
0 |
&phba->sli4_hba.nvmels_wq->pring->ring_lock |
|