Defined in 1 files as a prototype:

Defined in 1 files as a function:

Referenced in 1 files:

Smatch caller information:

drivers/pci/controller/mobiveil/pcie-mobiveil-host.c mobiveil_csr_writel() -> mobiveil_csr_write()

Type Parameter Key Value
PARAM_VALUE 0 pcie->rp.msi.dev_domain->msi_parent_ops->bus_select_token 0,3,5,9,12-13
PARAM_VALUE 2 off 4,24,1140,2056,2112,2240,2828,2844,2984
PARAM_VALUE 3 size 4
BUF_SIZE 0 pcie s32min-s32max
BUF_SIZE 0 pcie->ops (-1),8
BUF_SIZE 0 pcie->rp.bridge (-1),1984-3064
BUF_SIZE 0 pcie->rp.ops (-1),8
DATA_SOURCE 0 pcie $0
DATA_SOURCE 1 val $1
DATA_SOURCE 2 off $2
HARD_MAX 2 off 2984
PREEMPT_ADD
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HOST_DATA 1 val 0-u32max
UNITS 0 pcie unit_byte
HALF_LOCKED2 &rp->intx_mask_lock
HALF_LOCKED2 flags

drivers/pci/controller/mobiveil/pcie-mobiveil.c mobiveil_csr_writel() -> mobiveil_csr_write()

Type Parameter Key Value
PARAM_VALUE 0 pcie 4096-ptr_max
PARAM_VALUE 0 pcie->ib_wins_configured 0-1
PARAM_VALUE 0 pcie->pdev->dev.iommu->attach_deferred 0-1
PARAM_VALUE 0 pcie->rp.ob_io_res 4096-ptr_max
PARAM_VALUE 3 size 4
BUF_SIZE 0 pcie (-1)-1080
BUF_SIZE 0 pcie (-1)-1080
BUF_SIZE 0 pcie->ops (-1),8
BUF_SIZE 0 pcie->rp.bridge (-1),1984-3064
BUF_SIZE 0 pcie->rp.ops (-1),8
CAPPED_DATA 0 pcie->apio_wins 1
CAPPED_DATA 2 off 1
DATA_SOURCE 0 pcie $0
DATA_SOURCE 1 val $1
DATA_SOURCE 2 off $2
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HOST_DATA 1 val 0-u32max[c]
HALF_LOCKED2 &pool->lock

drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c mobiveil_csr_writel() -> mobiveil_csr_write()

Type Parameter Key Value
PARAM_VALUE 2 off 2828,2844
PARAM_VALUE 3 size 4
BUF_SIZE 0 pcie 360
DATA_SOURCE 0 pcie $0
DATA_SOURCE 1 val $1
DATA_SOURCE 2 off $2
HARD_MAX 2 off 2844
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HOST_DATA 1 val 1-u32max

drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c mobiveil_csr_writew() -> mobiveil_csr_write()

Type Parameter Key Value
PARAM_VALUE 0 pcie 4096-ptr_max
PARAM_VALUE 1 val 0-65471
PARAM_VALUE 2 off 62
PARAM_VALUE 3 size 2
BUF_SIZE 0 pcie 360
DATA_SOURCE 0 pcie $0
DATA_SOURCE 1 val $1
DATA_SOURCE 2 off $2
BIT_INFO 1 val 0x0,0xffbf
NOCHECK_CALL
HOST_DATA 1 val 0-65471[c]
HALF_LOCKED2 &pool->lock