mpc2_read_mpcc_state identifier - Linux source code next-20260811

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linux

Versions

FIXME
- FIXME
  - next-20260811

Defined in 1 files as a function:

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c, line 537 (as a function)

Referenced in 1 files:

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c, line 560

Smatch caller information:

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer_debug.c dcn10_get_mpcc_states() -> (struct mpc_funcs)->read_mpcc_state()

Type	Parameter	Key	Value
PARAM_VALUE	0	mpc	4096-ptr_max
PARAM_VALUE	0	mpc->funcs	4096-ptr_max
PARAM_VALUE	2	s	8362727815847772160
PARAM_VALUE	2	s->alpha_mode	0
PARAM_VALUE	2	s->bot_mpcc_id	0
PARAM_VALUE	2	s->busy	0
PARAM_VALUE	2	s->dpp_id	0
PARAM_VALUE	2	s->gamut_remap.gamut_adjust_type	0
PARAM_VALUE	2	s->gamut_remap.mpcc_gamut_remap_block_id	0
PARAM_VALUE	2	s->idle	0
PARAM_VALUE	2	s->lut3d_bit_depth	0
PARAM_VALUE	2	s->lut3d_mode	0
PARAM_VALUE	2	s->lut3d_size	0
PARAM_VALUE	2	s->mode	0
PARAM_VALUE	2	s->opp_id	0
PARAM_VALUE	2	s->overlap_only	0
PARAM_VALUE	2	s->pre_multiplied_alpha	0
PARAM_VALUE	2	s->rgam_lut	0
PARAM_VALUE	2	s->rgam_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_30bit_en	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_done	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_hard_underflow	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_soft_underflow	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_dis	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_force	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_state	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mode_cur	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_out_norm_factor	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_out_offset_r	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_out_scale_r	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_ram_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_read_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_size	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_wr_en_mask	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_cntl	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_lut_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_lut_write_en_mask	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_lut_write_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_dis	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_force	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_state	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mode_cur	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_offset_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_end_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_end_base_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_start_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_start_seg_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_scale_b	0
PARAM_VALUE	2	s->shaper_lut_mode	0
CAPPED_DATA	1	mpcc_inst	1
CONTAINER	0	*(-0-0+0)	$(-1)
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_resource.c acquire_resource_from_hw_enabled_state() -> (struct mpc_funcs)->read_mpcc_state()

Type	Parameter	Key	Value
PARAM_VALUE	0	mpc	4096-ptr_max
PARAM_VALUE	0	mpc->funcs	4096-ptr_max
PARAM_VALUE	0	mpc->funcs->read_mpcc_state	799385777705607168,3406652228445376512,4148742054592270336,4731192967292321792
PARAM_VALUE	2	s	844190324816371712
PARAM_VALUE	2	s->alpha_mode	0
PARAM_VALUE	2	s->bot_mpcc_id	0
PARAM_VALUE	2	s->busy	0
PARAM_VALUE	2	s->dpp_id	0
PARAM_VALUE	2	s->gamut_remap.gamut_adjust_type	0
PARAM_VALUE	2	s->gamut_remap.mpcc_gamut_remap_block_id	0
PARAM_VALUE	2	s->idle	0
PARAM_VALUE	2	s->lut3d_bit_depth	0
PARAM_VALUE	2	s->lut3d_mode	0
PARAM_VALUE	2	s->lut3d_size	0
PARAM_VALUE	2	s->mode	0
PARAM_VALUE	2	s->opp_id	0
PARAM_VALUE	2	s->overlap_only	0
PARAM_VALUE	2	s->pre_multiplied_alpha	0
PARAM_VALUE	2	s->rgam_lut	0
PARAM_VALUE	2	s->rgam_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_30bit_en	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_done	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_hard_underflow	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_soft_underflow	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_dis	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_force	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_state	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mode_cur	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_out_norm_factor	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_out_offset_r	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_out_scale_r	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_ram_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_read_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_size	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_wr_en_mask	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_cntl	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_lut_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_lut_write_en_mask	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_lut_write_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_dis	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_force	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_state	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mode_cur	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_offset_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_end_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_end_base_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_start_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_start_seg_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_scale_b	0
PARAM_VALUE	2	s->shaper_lut_mode	0
CONTAINER	0	*(-0-0+0)	$(-1)
TASK_NOT_RUNNING
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn10/dcn10_hwseq.c dcn10_log_color_state() -> (struct mpc_funcs)->read_mpcc_state()

Type	Parameter	Key	Value
PARAM_VALUE	0	mpc	4096-ptr_max
PARAM_VALUE	0	mpc->funcs	4096-ptr_max
PARAM_VALUE	2	s	8757798911096348672
PARAM_VALUE	2	s->alpha_mode	0
PARAM_VALUE	2	s->bot_mpcc_id	0
PARAM_VALUE	2	s->busy	0
PARAM_VALUE	2	s->dpp_id	0
PARAM_VALUE	2	s->gamut_remap.gamut_adjust_type	0
PARAM_VALUE	2	s->gamut_remap.mpcc_gamut_remap_block_id	0
PARAM_VALUE	2	s->idle	0
PARAM_VALUE	2	s->lut3d_bit_depth	0
PARAM_VALUE	2	s->lut3d_mode	0
PARAM_VALUE	2	s->lut3d_size	0
PARAM_VALUE	2	s->mode	0
PARAM_VALUE	2	s->opp_id	0
PARAM_VALUE	2	s->overlap_only	0
PARAM_VALUE	2	s->pre_multiplied_alpha	0
PARAM_VALUE	2	s->rgam_lut	0
PARAM_VALUE	2	s->rgam_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_30bit_en	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_done	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_hard_underflow	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_soft_underflow	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_dis	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_force	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_state	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mode_cur	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_out_norm_factor	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_out_offset_r	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_out_scale_r	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_ram_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_read_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_size	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_wr_en_mask	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_cntl	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_lut_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_lut_write_en_mask	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_lut_write_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_dis	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_force	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_state	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mode_cur	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_offset_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_end_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_end_base_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_start_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_start_seg_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_scale_b	0
PARAM_VALUE	2	s->shaper_lut_mode	0
CAPPED_DATA	1	mpcc_inst	1
CONTAINER	0	*(-0-0+0)	$(-1)
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn10/dcn10_hwseq.c dcn10_log_color_state() -> (struct mpc_funcs)->read_mpcc_state()

Type	Parameter	Key	Value
PARAM_VALUE	0	mpc	4096-ptr_max
PARAM_VALUE	0	mpc->funcs	4096-ptr_max
PARAM_VALUE	2	s	8757798911096348672
PARAM_VALUE	2	s->alpha_mode	0
PARAM_VALUE	2	s->bot_mpcc_id	0
PARAM_VALUE	2	s->busy	0
PARAM_VALUE	2	s->dpp_id	0
PARAM_VALUE	2	s->gamut_remap.gamut_adjust_type	0
PARAM_VALUE	2	s->gamut_remap.mpcc_gamut_remap_block_id	0
PARAM_VALUE	2	s->idle	0
PARAM_VALUE	2	s->lut3d_bit_depth	0
PARAM_VALUE	2	s->lut3d_mode	0
PARAM_VALUE	2	s->lut3d_size	0
PARAM_VALUE	2	s->mode	0
PARAM_VALUE	2	s->opp_id	0
PARAM_VALUE	2	s->overlap_only	0
PARAM_VALUE	2	s->pre_multiplied_alpha	0
PARAM_VALUE	2	s->rgam_lut	0
PARAM_VALUE	2	s->rgam_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_30bit_en	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_done	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_hard_underflow	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_soft_underflow	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_dis	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_force	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_state	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mode_cur	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_out_norm_factor	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_out_offset_r	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_out_scale_r	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_ram_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_read_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_size	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_wr_en_mask	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_cntl	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_lut_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_lut_write_en_mask	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_lut_write_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_dis	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_force	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_state	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mode_cur	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_offset_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_end_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_end_base_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_start_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_start_seg_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_scale_b	0
PARAM_VALUE	2	s->shaper_lut_mode	0
CAPPED_DATA	1	mpcc_inst	1
CONTAINER	0	*(-0-0+0)	$(-1)
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn10/dcn10_hwseq.c dcn10_log_color_state() -> (struct mpc_funcs)->read_mpcc_state()

Type	Parameter	Key	Value
PARAM_VALUE	0	mpc	4096-ptr_max
PARAM_VALUE	0	mpc->funcs	4096-ptr_max
PARAM_VALUE	2	s	8757798911096348672
PARAM_VALUE	2	s->alpha_mode	0
PARAM_VALUE	2	s->bot_mpcc_id	0
PARAM_VALUE	2	s->busy	0
PARAM_VALUE	2	s->dpp_id	0
PARAM_VALUE	2	s->gamut_remap.gamut_adjust_type	0
PARAM_VALUE	2	s->gamut_remap.mpcc_gamut_remap_block_id	0
PARAM_VALUE	2	s->idle	0
PARAM_VALUE	2	s->lut3d_bit_depth	0
PARAM_VALUE	2	s->lut3d_mode	0
PARAM_VALUE	2	s->lut3d_size	0
PARAM_VALUE	2	s->mode	0
PARAM_VALUE	2	s->opp_id	0
PARAM_VALUE	2	s->overlap_only	0
PARAM_VALUE	2	s->pre_multiplied_alpha	0
PARAM_VALUE	2	s->rgam_lut	0
PARAM_VALUE	2	s->rgam_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_30bit_en	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_done	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_hard_underflow	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_soft_underflow	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_dis	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_force	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_state	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mode_cur	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_out_norm_factor	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_out_offset_r	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_out_scale_r	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_ram_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_read_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_size	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_wr_en_mask	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_cntl	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_lut_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_lut_write_en_mask	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_lut_write_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_dis	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_force	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_state	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mode_cur	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_offset_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_end_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_end_base_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_start_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_start_seg_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_scale_b	0
PARAM_VALUE	2	s->shaper_lut_mode	0
CAPPED_DATA	1	mpcc_inst	1
CONTAINER	0	*(-0-0+0)	$(-1)
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn20/dcn20_hwseq.c dcn20_log_color_state() -> (struct mpc_funcs)->read_mpcc_state()

Type	Parameter	Key	Value
PARAM_VALUE	0	mpc	4096-ptr_max
PARAM_VALUE	0	mpc->funcs	4096-ptr_max
PARAM_VALUE	2	s	388582619308871680
PARAM_VALUE	2	s->alpha_mode	0
PARAM_VALUE	2	s->bot_mpcc_id	0
PARAM_VALUE	2	s->busy	0
PARAM_VALUE	2	s->dpp_id	0
PARAM_VALUE	2	s->gamut_remap.gamut_adjust_type	0
PARAM_VALUE	2	s->gamut_remap.mpcc_gamut_remap_block_id	0
PARAM_VALUE	2	s->idle	0
PARAM_VALUE	2	s->lut3d_bit_depth	0
PARAM_VALUE	2	s->lut3d_mode	0
PARAM_VALUE	2	s->lut3d_size	0
PARAM_VALUE	2	s->mode	0
PARAM_VALUE	2	s->opp_id	0
PARAM_VALUE	2	s->overlap_only	0
PARAM_VALUE	2	s->pre_multiplied_alpha	0
PARAM_VALUE	2	s->rgam_lut	0
PARAM_VALUE	2	s->rgam_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_30bit_en	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_done	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_hard_underflow	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_soft_underflow	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_dis	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_force	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_state	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mode_cur	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_out_norm_factor	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_out_offset_r	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_out_scale_r	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_ram_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_read_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_size	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_wr_en_mask	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_cntl	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_lut_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_lut_write_en_mask	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_lut_write_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_dis	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_force	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_state	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mode_cur	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_offset_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_end_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_end_base_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_start_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_start_seg_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_scale_b	0
PARAM_VALUE	2	s->shaper_lut_mode	0
CAPPED_DATA	1	mpcc_inst	1
CONTAINER	0	*(-0-0+0)	$(-1)
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn30/dcn30_hwseq.c dcn30_log_color_state() -> (struct mpc_funcs)->read_mpcc_state()

Type	Parameter	Key	Value
PARAM_VALUE	0	mpc	4096-ptr_max
PARAM_VALUE	0	mpc->funcs	4096-ptr_max
PARAM_VALUE	2	s	3563939268923920384
PARAM_VALUE	2	s->alpha_mode	0
PARAM_VALUE	2	s->bot_mpcc_id	0
PARAM_VALUE	2	s->busy	0
PARAM_VALUE	2	s->dpp_id	0
PARAM_VALUE	2	s->gamut_remap.gamut_adjust_type	0
PARAM_VALUE	2	s->gamut_remap.mpcc_gamut_remap_block_id	0
PARAM_VALUE	2	s->idle	0
PARAM_VALUE	2	s->lut3d_bit_depth	0
PARAM_VALUE	2	s->lut3d_mode	0
PARAM_VALUE	2	s->lut3d_size	0
PARAM_VALUE	2	s->mode	0
PARAM_VALUE	2	s->opp_id	0
PARAM_VALUE	2	s->overlap_only	0
PARAM_VALUE	2	s->pre_multiplied_alpha	0
PARAM_VALUE	2	s->rgam_lut	0
PARAM_VALUE	2	s->rgam_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_30bit_en	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_done	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_hard_underflow	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_fl_soft_underflow	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_dis	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_force	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mem_pwr_state	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_mode_cur	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_out_norm_factor	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_out_offset_r	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_out_scale_r	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_ram_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_read_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_size	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_3dlut_wr_en_mask	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_cntl	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_lut_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_lut_write_en_mask	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_lut_write_sel	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_dis	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_force	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_mode	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mem_pwr_state	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_mode_cur	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_offset_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_end_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_end_base_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_start_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_rama_exp_region_start_seg_b	0
PARAM_VALUE	2	s->rmcm_regs.rmcm_shaper_scale_b	0
PARAM_VALUE	2	s->shaper_lut_mode	0
CAPPED_DATA	1	mpcc_inst	1
CONTAINER	0	*(-0-0+0)	$(-1)
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL