Open Menu /

Defined in 1 files as a function:

Referenced in 1 files:

Smatch caller information:

drivers/net/wireless/mediatek/mt76/npu.c mt76_npu_dequeue() -> mt76_dma_handle_write()

Type Parameter Key Value
PARAM_VALUE 0 q 4096-ptr_max
PARAM_VALUE 0 q->desc 4096-ptr_max
PARAM_VALUE 0 q->entry 4096-ptr_max
PARAM_VALUE 0 q->page_pool 4096-ptr_max
PARAM_VALUE 1 offset 12
CAPPED_DATA 0 q->tail 1
CAPPED_DATA 2 val 1
DATA_SOURCE 0 q $1
RX_PATH
TASK_NOT_RUNNING
UNITS 2 val unit_array_size
LOCK2 rcu_read
HALF_LOCKED2 bh

drivers/net/wireless/mediatek/mt76/dma.c mt76_dma_kick_queue() -> mt76_dma_handle_write()

Type Parameter Key Value
PARAM_VALUE 0 q 4096-ptr_max
PARAM_VALUE 1 offset 8
BUF_SIZE 0 q (-1),528,792,1056,1320,1584,1848,2112,2376,2640,2904,3168,3432,3696,3960,4224,4488,4752,5016,5280,5544
BUF_SIZE 0 q (-1),528,792,1056,1320,1584,1848,2112,2376,2640,2904,3168,3432,3696,3960,4224,4488,4752,5016,5280,5544
BUF_SIZE 0 q->rx_head (-1)-s32max
BUF_SIZE 0 q->wed (-1)-0,9192
DATA_SOURCE 0 q $1
PREEMPT_ADD
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 q->dev->mmio.irqmask 0-u32max[c]
HOST_DATA 0 q->dev->rx_token.idr_rt.xa_flags 0-u32max
HOST_DATA 0 q->dev->rxfilter 0-u32max
HOST_DATA 0 q->dev->token.idr_rt.xa_flags 0,67108864-u32max
HOST_DATA 0 q->head 0-u16max
HOST_DATA 0 q->tail 0-u16max
HOST_DATA 0 *q->emi_cpu_idx 0-u16max
HOST_DATA 2 val 0-u16max
UNITS 2 val unit_array_size
USER_PTR 0 q->rx_head->data
HALF_LOCKED2 &mdev->mcu.mutex
HALF_LOCKED2 bh
HALF_LOCKED2 rcu_read
HALF_LOCKED2 0 &q->lock

drivers/net/wireless/mediatek/mt76/dma.c mt76_dma_queue_reset() -> mt76_dma_handle_write()

Type Parameter Key Value
PARAM_VALUE 0 q 4096-ptr_max
PARAM_VALUE 0 q->ndesc s32min-(-1),1-s32max
PARAM_VALUE 0 q->page_pool->p.dev->dma_io_tlb_mem->can_grow 0-1
PARAM_VALUE 1 offset 8
PARAM_VALUE 2 val 0
BUF_SIZE 0 q (-1),264,528,792,1056,1320,1584,1848,2112,2376,2640,2904,3168,3432,3696,3960,4224,4488,4752,5016,5280,5544
BUF_SIZE 0 q (-1),264,528,792,1056,1320,1584,1848,2112,2376,2640,2904,3168,3432,3696,3960,4224,4488,4752,5016,5280,5544
BUF_SIZE 0 q->wed (-1)-0,9192
CAPPED_DATA 0 q->ndesc 1
DATA_SOURCE 0 q $1
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 q->dev->mmio.irqmask 0-u32max[c]
HOST_DATA 0 q->dev->rx_token.idr_rt.xa_flags 0-u32max
HOST_DATA 0 q->dev->rxfilter 0-u32max
HOST_DATA 0 q->dev->token.idr_rt.xa_flags 0,67108864-u32max
HOST_DATA 0 q->head 0-u16max
HOST_DATA 0 q->tail 0-u16max
HALF_LOCKED2 &dev->mt76.mutex
HALF_LOCKED2 &pool->lock

drivers/net/wireless/mediatek/mt76/dma.c mt76_dma_queue_reset() -> mt76_dma_handle_write()

Type Parameter Key Value
PARAM_VALUE 0 q 4096-ptr_max
PARAM_VALUE 0 q->ndesc s32min-(-1),1-s32max
PARAM_VALUE 0 q->page_pool->p.dev->dma_io_tlb_mem->can_grow 0-1
PARAM_VALUE 1 offset 12
PARAM_VALUE 2 val 0
BUF_SIZE 0 q (-1),264,528,792,1056,1320,1584,1848,2112,2376,2640,2904,3168,3432,3696,3960,4224,4488,4752,5016,5280,5544
BUF_SIZE 0 q (-1),264,528,792,1056,1320,1584,1848,2112,2376,2640,2904,3168,3432,3696,3960,4224,4488,4752,5016,5280,5544
BUF_SIZE 0 q->wed (-1)-0,9192
CAPPED_DATA 0 q->ndesc 1
DATA_SOURCE 0 q $1
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 q->dev->mmio.irqmask 0-u32max[c]
HOST_DATA 0 q->dev->rx_token.idr_rt.xa_flags 0-u32max
HOST_DATA 0 q->dev->rxfilter 0-u32max
HOST_DATA 0 q->dev->token.idr_rt.xa_flags 0,67108864-u32max
HOST_DATA 0 q->head 0-u16max
HOST_DATA 0 q->tail 0-u16max
HALF_LOCKED2 &dev->mt76.mutex
HALF_LOCKED2 &pool->lock

drivers/net/wireless/mediatek/mt76/dma.c mt76_dma_sync_idx() -> mt76_dma_handle_write()

Type Parameter Key Value
PARAM_VALUE 0 q 4096-ptr_max
PARAM_VALUE 0 q->page_pool->p.dev->dma_io_tlb_mem->can_grow 0-1
PARAM_VALUE 1 offset 4
BUF_SIZE 0 q (-1),528,792,1056,1320,1584,1848,2112,2376,2640,2904,3168,3432,3696,3960,4224,4488,4752,5016,5280,5544
BUF_SIZE 0 q (-1),528,792,1056,1320,1584,1848,2112,2376,2640,2904,3168,3432,3696,3960,4224,4488,4752,5016,5280,5544
BUF_SIZE 0 q->wed (-1)-0,9192
DATA_SOURCE 0 q $1
BIT_INFO 0 q->flags 0x80,0xffff
BIT_INFO 2 val 0x2000,0x7fffffff
PREEMPT_ADD
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 q->dev->mmio.irqmask 0-u32max[c]
HOST_DATA 0 q->dev->rx_token.idr_rt.xa_flags 0-u32max
HOST_DATA 0 q->dev->rxfilter 0-u32max
HOST_DATA 0 q->dev->token.idr_rt.xa_flags 0,67108864-u32max
HOST_DATA 0 q->head 0-u16max
HOST_DATA 0 q->tail 0-u16max
HALF_LOCKED2 &dev->mt76.mutex
HALF_LOCKED2 &pool->lock
HALF_LOCKED2 bh
HALF_LOCKED2 0 &q->lock

drivers/net/wireless/mediatek/mt76/dma.c mt76_dma_sync_idx() -> mt76_dma_handle_write()

Type Parameter Key Value
PARAM_VALUE 0 q 4096-ptr_max
PARAM_VALUE 0 q->page_pool->p.dev->dma_io_tlb_mem->can_grow 0-1
PARAM_VALUE 1 offset 4
BUF_SIZE 0 q (-1),528,792,1056,1320,1584,1848,2112,2376,2640,2904,3168,3432,3696,3960,4224,4488,4752,5016,5280,5544
BUF_SIZE 0 q (-1),528,792,1056,1320,1584,1848,2112,2376,2640,2904,3168,3432,3696,3960,4224,4488,4752,5016,5280,5544
BUF_SIZE 0 q->wed (-1)-0,9192
DATA_SOURCE 0 q $1
BIT_INFO 0 q->flags 0x0,0xffff
PREEMPT_ADD
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 q->dev->mmio.irqmask 0-u32max[c]
HOST_DATA 0 q->dev->rx_token.idr_rt.xa_flags 0-u32max
HOST_DATA 0 q->dev->rxfilter 0-u32max
HOST_DATA 0 q->dev->token.idr_rt.xa_flags 0,67108864-u32max
HOST_DATA 0 q->head 0-u16max
HOST_DATA 0 q->tail 0-u16max
UNITS 2 val unit_array_size
HALF_LOCKED2 &dev->mt76.mutex
HALF_LOCKED2 &pool->lock
HALF_LOCKED2 bh
HALF_LOCKED2 0 &q->lock

drivers/net/wireless/mediatek/mt76/dma.c mt76_dma_sync_idx() -> mt76_dma_handle_write()

Type Parameter Key Value
PARAM_VALUE 0 q 4096-ptr_max
PARAM_VALUE 0 q->page_pool->p.dev->dma_io_tlb_mem->can_grow 0-1
PARAM_VALUE 1 offset 0
BUF_SIZE 0 q (-1),528,792,1056,1320,1584,1848,2112,2376,2640,2904,3168,3432,3696,3960,4224,4488,4752,5016,5280,5544
BUF_SIZE 0 q (-1),528,792,1056,1320,1584,1848,2112,2376,2640,2904,3168,3432,3696,3960,4224,4488,4752,5016,5280,5544
BUF_SIZE 0 q->wed (-1)-0,9192
DATA_SOURCE 0 q $1
BIT_INFO 0 q->flags 0x0,0xffff
PREEMPT_ADD
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 q->dev->mmio.irqmask 0-u32max[c]
HOST_DATA 0 q->dev->rx_token.idr_rt.xa_flags 0-u32max
HOST_DATA 0 q->dev->rxfilter 0-u32max
HOST_DATA 0 q->dev->token.idr_rt.xa_flags 0,67108864-u32max
HOST_DATA 0 q->head 0-u16max
HOST_DATA 0 q->tail 0-u16max
HALF_LOCKED2 &dev->mt76.mutex
HALF_LOCKED2 &pool->lock
HALF_LOCKED2 bh
HALF_LOCKED2 0 &q->lock