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Defined in 1 files as a function:

Referenced in 1 files:

Smatch caller information:

drivers/net/wireless/mediatek/mt76/mt76x02_mmio.c mt76x02_pre_tbtt_tasklet() -> (struct mt76_queue_ops)->tx_queue_skb()

Type Parameter Key Value
PARAM_VALUE 0 phy 4096-ptr_max
PARAM_VALUE 0 phy->offchannel 0
PARAM_VALUE 1 q 4096-ptr_max
PARAM_VALUE 1 q->lock.rlock.dep_map->name 0-255
PARAM_VALUE 2 qid 4
PARAM_VALUE 3 skb 4096-281621011281215496
PARAM_VALUE 3 skb->next 0
PARAM_VALUE 3 skb->prev 0
PARAM_VALUE 5 sta 0
DATA_SOURCE 3 skb r __skb_dequeue
CONTAINER 0 -16-23360-0+0 $(-1)
TASK_NOT_RUNNING
NOCHECK_CALL
LOCK2 1 &q->lock
HALF_LOCKED2 bh
TYPE_LOCK (struct mt76_queue)->lock

drivers/net/wireless/mediatek/mt76/tx.c __mt76_tx_queue_skb() -> (struct mt76_queue_ops)->tx_queue_skb()

Type Parameter Key Value
PARAM_VALUE 0 phy 4096-ptr_max
PARAM_VALUE 0 phy->dev 4096-ptr_max
PARAM_VALUE 0 phy->dev->drv->link_data_size 0-4000000
PARAM_VALUE 0 phy->dev->drv->vif_link_add 0,5984001547580555264
PARAM_VALUE 0 phy->dev->queue_ops 4096-ptr_max
PARAM_VALUE 0 phy->dev->queue_ops->tx_queue_skb 4096-ptr_max
PARAM_VALUE 0 phy->dev->tx_worker.task->sched_class->set_cpus_allowed 0,1927640468783054848,5094656021401329664,7127180339355369472
PARAM_VALUE 0 phy->q_tx 4096-ptr_max
PARAM_VALUE 2 qid 0-u16max
PARAM_VALUE 3 skb 4096-ptr_max
PARAM_VALUE 3 skb->cb 4096-ptr_max
BUF_SIZE 0 phy (-1),2952
BUF_SIZE 0 phy (-1),2952
BUF_SIZE 0 phy->chanctx (-1),72
BUF_SIZE 0 phy->roc_link (-1)-0,2216
BUF_SIZE 4 wcid (-1),248
BUF_SIZE 4 wcid (-1),248
DATA_SOURCE 0 phy $0
DATA_SOURCE 2 qid $1
DATA_SOURCE 3 skb $2
DATA_SOURCE 4 wcid $3
DATA_SOURCE 5 sta $4
TASK_NOT_RUNNING
NO_OVERFLOW_SIMPLE 0 phy->roc_vif->active_links
LOCK2 bh
HALF_LOCKED2 &hwq->lock
HALF_LOCKED2 &q->lock
HALF_LOCKED2 rcu_read
TYPE_LOCK (struct mt76_queue)->lock

drivers/net/wireless/mediatek/mt76/testmode.c mt76_testmode_tx_pending() -> (struct mt76_queue_ops)->tx_queue_skb()

Type Parameter Key Value
PARAM_VALUE 0 phy 4096-ptr_max
PARAM_VALUE 0 phy->dev->queue_ops 4096-ptr_max
PARAM_VALUE 0 phy->q_tx 4096-ptr_max
PARAM_VALUE 0 phy->test.tx_pending 1-u32max
PARAM_VALUE 1 q 4096-ptr_max
PARAM_VALUE 1 q->lock.rlock.dep_map->name 0-255
PARAM_VALUE 1 q->queued s32min-2147483646
PARAM_VALUE 2 qid 0-u16max
PARAM_VALUE 3 skb 4096-ptr_max
PARAM_VALUE 4 wcid 4096-ptr_max
PARAM_VALUE 5 sta 0
BUF_SIZE 4 wcid 1024
CAPPED_DATA 1 q->queued 1
DATA_SOURCE 0 phy $0
FUZZY_MAX 0 phy->test.tx_pending 1
CONTAINER 4 -16-23360+24632 $(-1)
LOCK2 bh
LOCK2 1 &q->lock
TYPE_LOCK (struct mt76_queue)->lock

drivers/net/wireless/mediatek/mt76/mt7603/beacon.c mt7603_pre_tbtt_tasklet() -> (struct mt76_queue_ops)->tx_queue_skb()

Type Parameter Key Value
PARAM_VALUE 0 phy 4096-ptr_max
PARAM_VALUE 0 phy->offchannel 0
PARAM_VALUE 1 q 4096-ptr_max
PARAM_VALUE 1 q->lock.rlock.dep_map->name 0-255
PARAM_VALUE 2 qid 6
PARAM_VALUE 3 skb 4096-1761798546132013064
PARAM_VALUE 3 skb->next 0
PARAM_VALUE 3 skb->prev 0
PARAM_VALUE 5 sta 0
DATA_SOURCE 3 skb r __skb_dequeue
CONTAINER 0 -16-23360-0+0 $(-1)
TASK_NOT_RUNNING
NOCHECK_CALL
LOCK2 1 &q->lock
HALF_LOCKED2 bh
TYPE_LOCK (struct mt76_queue)->lock

drivers/net/wireless/mediatek/mt76/mt7603/beacon.c mt7603_update_beacon_iter() -> (struct mt76_queue_ops)->tx_queue_skb()

Type Parameter Key Value
PARAM_VALUE 0 phy 4096-ptr_max
PARAM_VALUE 2 qid 5
PARAM_VALUE 3 skb 4096-ptr_max
PARAM_VALUE 4 wcid 4096-ptr_max
PARAM_VALUE 5 sta 0
BUF_SIZE 3 skb (-1)-s32max
BUF_SIZE 3 skb (-1)-s32max
CAPPED_DATA 3 skb 1
DATA_SOURCE 3 skb r ieee80211_beacon_get
CONTAINER 0 -16-23360-0+0 $(-1)
TASK_NOT_RUNNING
NOCHECK_CALL
USER_DATA 0 phy->antenna_mask 0-255[u]
USER_DATA 0 phy->band_idx 0-255[u]
USER_DATA 0 phy->cap.has_2ghz 0-1[u]
USER_DATA 0 phy->cap.has_5ghz 0-1[u]
USER_DATA 0 phy->cap.has_6ghz 0-1[u]
USER_DATA 0 phy->chainmask 0-u16max[u]
USER_DATA 0 phy->chandef.center_freq1 0-u32max[u]
USER_DATA 0 phy->chandef.center_freq2 0-u32max[u]
USER_DATA 0 phy->chandef.edmg.bw_config 0-u32max[u]
USER_DATA 0 phy->chandef.edmg.channels 0-255[u]
USER_DATA 0 phy->chandef.freq1_offset 0-u16max[u]
USER_DATA 0 phy->chandef.npca_punctured 0-u16max[u]
USER_DATA 0 phy->chandef.punctured 0-u16max[u]
USER_DATA 0 phy->chandef.s1g_primary_2mhz 0-1[u]
USER_DATA 0 phy->chandef.width 0-u32max[u]
USER_DATA 0 phy->dfs_state 0-u32max[u]
USER_DATA 0 phy->leds.al 0-1[u]
USER_DATA 0 phy->leds.cdev.activated 0-1[u]
USER_DATA 0 phy->leds.cdev.blink_brightness s32min-s32max[u]
USER_DATA 0 phy->leds.cdev.blink_delay_off 0-u64max[u]
USER_DATA 0 phy->leds.cdev.blink_delay_on 0-u64max[u]
USER_DATA 0 phy->leds.cdev.blink_timer.expires 0-u64max[u]
USER_DATA 0 phy->leds.cdev.blink_timer.flags 0-u32max[u]
USER_DATA 0 phy->leds.cdev.brightness 0-u32max[u]
USER_DATA 0 phy->leds.cdev.brightness_hw_changed s32min-s32max[u]
USER_DATA 0 phy->leds.cdev.color 0-u32max[u]
USER_DATA 0 phy->leds.cdev.delayed_delay_off 0-u64max[u]
USER_DATA 0 phy->leds.cdev.delayed_delay_on 0-u64max[u]
USER_DATA 0 phy->leds.cdev.delayed_set_value s32min-s32max[u]
USER_DATA 0 phy->leds.cdev.flags s32min-s32max[u]
USER_DATA 0 phy->leds.cdev.led_access.osq.tail.counter s32min-s32max[u]
USER_DATA 0 phy->leds.cdev.led_access.owner.counter s64min-s64max[u]
USER_DATA 0 phy->leds.cdev.max_brightness 0-u32max[u]
USER_DATA 0 phy->leds.cdev.new_blink_brightness s32min-s32max[u]
USER_DATA 0 phy->leds.cdev.set_brightness_work.data.counter s64min-s64max[u]
USER_DATA 0 phy->leds.cdev.trigger_lock.count.counter s64min-s64max[u]
USER_DATA 0 phy->leds.cdev.trigger_lock.osq.tail.counter s32min-s32max[u]
USER_DATA 0 phy->leds.cdev.trigger_lock.owner.counter s64min-s64max[u]
USER_DATA 0 phy->leds.cdev.work_flags 0-u64max[u]
USER_DATA 0 phy->leds.pin 0-255[u]
USER_DATA 0 phy->mac_work.cpu s32min-s32max[u]
USER_DATA 0 phy->mac_work.timer.expires 0-u64max[u]
USER_DATA 0 phy->mac_work.timer.flags 0-u32max[u]
USER_DATA 0 phy->mac_work.work.data.counter s64min-s64max[u]
USER_DATA 0 phy->mac_work_count 0-255[u]
USER_DATA 0 phy->main_chandef.center_freq1 0-u32max[u]
USER_DATA 0 phy->main_chandef.center_freq2 0-u32max[u]
USER_DATA 0 phy->main_chandef.edmg.bw_config 0-u32max[u]
USER_DATA 0 phy->main_chandef.edmg.channels 0-255[u]
USER_DATA 0 phy->main_chandef.freq1_offset 0-u16max[u]
USER_DATA 0 phy->main_chandef.npca_punctured 0-u16max[u]
USER_DATA 0 phy->main_chandef.punctured 0-u16max[u]
USER_DATA 0 phy->main_chandef.s1g_primary_2mhz 0-1[u]
USER_DATA 0 phy->main_chandef.width 0-u32max[u]
USER_DATA 0 phy->mgmt_tx_pending.counter s32min-s32max[u]
USER_DATA 0 phy->no_active_monitor 0-1[u]
USER_DATA 0 phy->num_sta 0-u32max[u]
USER_DATA 0 phy->offchannel 0-1[u]
USER_DATA 0 phy->radar_enabled 0-1[u]
USER_DATA 0 phy->roc_work.cpu s32min-s32max[u]
USER_DATA 0 phy->roc_work.timer.expires 0-u64max[u]
USER_DATA 0 phy->roc_work.timer.flags 0-u32max[u]
USER_DATA 0 phy->roc_work.work.data.counter s64min-s64max[u]
USER_DATA 0 phy->sband_2g.sband.band 0-u32max[u]
USER_DATA 0 phy->sband_2g.sband.edmg_cap.bw_config 0-u32max[u]
USER_DATA 0 phy->sband_2g.sband.edmg_cap.channels 0-255[u]
USER_DATA 0 phy->sband_2g.sband.ht_cap.ampdu_density 0-255[u]
USER_DATA 0 phy->sband_2g.sband.ht_cap.ampdu_factor 0-255[u]
USER_DATA 0 phy->sband_2g.sband.ht_cap.cap 0-u16max[u]
USER_DATA 0 phy->sband_2g.sband.ht_cap.ht_supported 0-1[u]
USER_DATA 0 phy->sband_2g.sband.ht_cap.mcs.rx_highest 0-u16max[u]
USER_DATA 0 phy->sband_2g.sband.ht_cap.mcs.tx_params 0-255[u]
USER_DATA 0 phy->sband_2g.sband.n_bitrates s32min-s32max[u]
USER_DATA 0 phy->sband_2g.sband.n_channels s32min-s32max[u]
USER_DATA 0 phy->sband_2g.sband.n_iftype_data 0-u16max[u]
USER_DATA 0 phy->sband_2g.sband.s1g_cap.s1g 0-1[u]
USER_DATA 0 phy->sband_2g.sband.vht_cap.cap 0-u32max[u]
USER_DATA 0 phy->sband_2g.sband.vht_cap.vht_mcs.rx_highest 0-u16max[u]
USER_DATA 0 phy->sband_2g.sband.vht_cap.vht_mcs.rx_mcs_map 0-u16max[u]
USER_DATA 0 phy->sband_2g.sband.vht_cap.vht_mcs.tx_highest 0-u16max[u]
USER_DATA 0 phy->sband_2g.sband.vht_cap.vht_mcs.tx_mcs_map 0-u16max[u]
USER_DATA 0 phy->sband_2g.sband.vht_cap.vht_supported 0-1[u]
USER_DATA 0 phy->sband_5g.sband.band 0-u32max[u]
USER_DATA 0 phy->sband_5g.sband.edmg_cap.bw_config 0-u32max[u]
USER_DATA 0 phy->sband_5g.sband.edmg_cap.channels 0-255[u]
USER_DATA 0 phy->sband_5g.sband.ht_cap.ampdu_density 0-255[u]
USER_DATA 0 phy->sband_5g.sband.ht_cap.ampdu_factor 0-255[u]
USER_DATA 0 phy->sband_5g.sband.ht_cap.cap 0-u16max[u]
USER_DATA 0 phy->sband_5g.sband.ht_cap.ht_supported 0-1[u]
USER_DATA 0 phy->sband_5g.sband.ht_cap.mcs.rx_highest 0-u16max[u]
USER_DATA 0 phy->sband_5g.sband.ht_cap.mcs.tx_params 0-255[u]
USER_DATA 0 phy->sband_5g.sband.n_bitrates s32min-s32max[u]
USER_DATA 0 phy->sband_5g.sband.n_channels s32min-s32max[u]
USER_DATA 0 phy->sband_5g.sband.n_iftype_data 0-u16max[u]
USER_DATA 0 phy->sband_5g.sband.s1g_cap.s1g 0-1[u]
USER_DATA 0 phy->sband_5g.sband.vht_cap.cap 0-u32max[u]
USER_DATA 0 phy->sband_5g.sband.vht_cap.vht_mcs.rx_highest 0-u16max[u]
USER_DATA 0 phy->sband_5g.sband.vht_cap.vht_mcs.rx_mcs_map 0-u16max[u]
USER_DATA 0 phy->sband_5g.sband.vht_cap.vht_mcs.tx_highest 0-u16max[u]
USER_DATA 0 phy->sband_5g.sband.vht_cap.vht_mcs.tx_mcs_map 0-u16max[u]
USER_DATA 0 phy->sband_5g.sband.vht_cap.vht_supported 0-1[u]
USER_DATA 0 phy->sband_6g.sband.band 0-u32max[u]
USER_DATA 0 phy->sband_6g.sband.edmg_cap.bw_config 0-u32max[u]
USER_DATA 0 phy->sband_6g.sband.edmg_cap.channels 0-255[u]
USER_DATA 0 phy->sband_6g.sband.ht_cap.ampdu_density 0-255[u]
USER_DATA 0 phy->sband_6g.sband.ht_cap.ampdu_factor 0-255[u]
USER_DATA 0 phy->sband_6g.sband.ht_cap.cap 0-u16max[u]
USER_DATA 0 phy->sband_6g.sband.ht_cap.ht_supported 0-1[u]
USER_DATA 0 phy->sband_6g.sband.ht_cap.mcs.rx_highest 0-u16max[u]
USER_DATA 0 phy->sband_6g.sband.ht_cap.mcs.tx_params 0-255[u]
USER_DATA 0 phy->sband_6g.sband.n_bitrates s32min-s32max[u]
USER_DATA 0 phy->sband_6g.sband.n_channels s32min-s32max[u]
USER_DATA 0 phy->sband_6g.sband.n_iftype_data 0-u16max[u]
USER_DATA 0 phy->sband_6g.sband.s1g_cap.s1g 0-1[u]
USER_DATA 0 phy->sband_6g.sband.vht_cap.cap 0-u32max[u]
USER_DATA 0 phy->sband_6g.sband.vht_cap.vht_mcs.rx_highest 0-u16max[u]
USER_DATA 0 phy->sband_6g.sband.vht_cap.vht_mcs.rx_mcs_map 0-u16max[u]
USER_DATA 0 phy->sband_6g.sband.vht_cap.vht_mcs.tx_highest 0-u16max[u]
USER_DATA 0 phy->sband_6g.sband.vht_cap.vht_mcs.tx_mcs_map 0-u16max[u]
USER_DATA 0 phy->sband_6g.sband.vht_cap.vht_supported 0-1[u]
USER_DATA 0 phy->state 0-u64max[u]
USER_DATA 0 phy->survey_time s64min-s64max[u]
USER_DATA 0 phy->test.freq_offset 0-u32max[u]
USER_DATA 0 phy->test.state 0-u32max[u]
USER_DATA 0 phy->test.tx_antenna_mask 0-255[u]
USER_DATA 0 phy->test.tx_count 0-u32max[u]
USER_DATA 0 phy->test.tx_done 0-u32max[u]
USER_DATA 0 phy->test.tx_duty_cycle 0-255[u]
USER_DATA 0 phy->test.tx_ipg 0-u32max[u]
USER_DATA 0 phy->test.tx_ltf 0-255[u]
USER_DATA 0 phy->test.tx_mpdu_len 0-u16max[u]
USER_DATA 0 phy->test.tx_pending 0-u32max[u]
USER_DATA 0 phy->test.tx_power_control 0-255[u]
USER_DATA 0 phy->test.tx_queued 0-u32max[u]
USER_DATA 0 phy->test.tx_queued_limit 0-u16max[u]
USER_DATA 0 phy->test.tx_rate_idx 0-255[u]
USER_DATA 0 phy->test.tx_rate_ldpc 0-255[u]
USER_DATA 0 phy->test.tx_rate_mode 0-255[u]
USER_DATA 0 phy->test.tx_rate_nss 0-255[u]
USER_DATA 0 phy->test.tx_rate_sgi 0-255[u]
USER_DATA 0 phy->test.tx_rate_stbc 0-255[u]
USER_DATA 0 phy->test.tx_spe_idx 0-255[u]
USER_DATA 0 phy->test.tx_time 0-u32max[u]
USER_DATA 0 phy->txpower_cur s32min-s32max[u]
LOCK2 &dev->ps_lock
LOCK2 bh
HALF_LOCKED2 &dev->mt76.mutex
HALF_LOCKED2 &local->iflist_mtx
HALF_LOCKED2 &mvm->mutex
HALF_LOCKED2 &pool->lock
HALF_LOCKED2 rcu_read
TYPE_LOCK (struct mt7603_dev)->ps_lock