Defined in 1 files as a function:
Referenced in 1 files:
Smatch caller information:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml2_0/dml2_wrapper_fpu.c calculate_lowest_supported_state_for_temp_read() -> pack_and_call_dml_mode_support_ex()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dml2 | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy->ImmediateFlipRequirement | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy->MPCCombineUse | 2 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy->ODMUse | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.AllowForPStateChangeOrStutterInVBlankFinal | 0-1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.DRAMClockChangeRequirementFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.FCLKChangeRequirementFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.SynchronizeDRRDisplaysForUCLKPStateChangeFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.SynchronizeTimingsFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.USRRetrainingRequiredFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.UseOnlyMaxPrefetchModes | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.states.num_states | 0-s32max |
| PARAM_VALUE | 0 | *dml2->v20.dml_core_ctx.policy.ODMUse | 2,4 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid | 0-1 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid | 0-1 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id | 0-4294967295 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid | 0-1 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.hpo_stream_to_link_encoder_mapping | s32min-s32max |
| PARAM_VALUE | 1 | display_cfg | 4096-ptr_max |
| PARAM_VALUE | 1 | display_cfg->num_surfaces | 0-s32max |
| PARAM_VALUE | 1 | display_cfg->num_timings | 0-s32max |
| PARAM_VALUE | 2 | evaluation_info | 4096-ptr_max |
| PARAM_VALUE | 2 | evaluation_info->ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified | 0 |
| CAPPED_DATA | 0 | dml2->config.dcn_pipe_count | 1 |
| CAPPED_DATA | 0 | dml2->v20.dml_core_ctx.states.num_states | 1 |
| DATA_SOURCE | 0 | dml2 | $0 |
| DATA_SOURCE | 3 | validate_mode | $2 |
| MEM_ZERO | 1 | display_cfg | |
| MEM_ZERO | 2 | evaluation_info |
drivers/gpu/drm/amd/amdgpu/../display/dc/dml2_0/dml2_wrapper_fpu.c dml2_validate_only() -> pack_and_call_dml_mode_support_ex()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dml2 | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy->ImmediateFlipRequirement | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy->MPCCombineUse | 2 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy->ODMUse | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.AllowForPStateChangeOrStutterInVBlankFinal | 0-1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.DRAMClockChangeRequirementFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.FCLKChangeRequirementFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.SynchronizeDRRDisplaysForUCLKPStateChangeFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.SynchronizeTimingsFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.USRRetrainingRequiredFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.UseOnlyMaxPrefetchModes | 1 |
| PARAM_VALUE | 0 | dml2->v20.scratch.cur_display_config->plane.BlendingAndTiming | 0-s32max |
| PARAM_VALUE | 0 | dml2->v20.scratch.cur_display_config->plane.UseMALLForPStateChange | 0,2-3 |
| PARAM_VALUE | 0 | dml2->v20.scratch.cur_display_config->plane.UseMALLForStaticScreen | 0,2 |
| PARAM_VALUE | 0 | dml2->v20.scratch.cur_display_config.num_surfaces | 1-s32max |
| PARAM_VALUE | 0 | dml2->v20.scratch.cur_display_config.num_timings | 1-s32max |
| PARAM_VALUE | 0 | *dml2->v20.dml_core_ctx.policy.ODMUse | 2,4 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.cur_display_config.output.OutputBpp | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.cur_display_config.output.PixelClockBackEnd | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.cur_display_config.plane.HRatio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.cur_display_config.plane.HRatioChroma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.cur_display_config.plane.VRatio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.cur_display_config.plane.VRatioChroma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.cur_display_config.surface.DCCFractionOfZeroSizeRequestsChroma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.cur_display_config.surface.DCCFractionOfZeroSizeRequestsLuma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.cur_display_config.surface.DCCRateChroma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.cur_display_config.surface.DCCRateLuma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.cur_display_config.timing.PixelClock | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.cur_display_config.writeback.WritebackHRatio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.cur_display_config.writeback.WritebackVRatio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid | 0-1 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid | 0-1 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id | 0-4294967295 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid | 0-1 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.hpo_stream_to_link_encoder_mapping | s32min-s32max |
| PARAM_VALUE | 1 | display_cfg | 4096-ptr_max |
| PARAM_VALUE | 1 | display_cfg->num_surfaces | 1-s32max |
| PARAM_VALUE | 1 | display_cfg->num_timings | 1-s32max |
| PARAM_VALUE | 2 | evaluation_info | 4096-ptr_max |
| PARAM_VALUE | 3 | validate_mode | 1 |
| DATA_SOURCE | 3 | validate_mode | $1 |
| MEM_ZERO | 0 | &dml2->v20.dml_core_ctx.mp | |
| MEM_ZERO | 0 | &dml2->v20.dml_core_ctx.ms | |
| MEM_ZERO | 0 | &dml2->v20.dml_core_ctx.policy | |
| MEM_ZERO | 0 | &dml2->v20.scratch | |
| MEM_ZERO | 1 | display_cfg | |
| MEM_ZERO | 2 | evaluation_info | |
| PREEMPT_ADD | |||
| RX_PATH | |||
| TASK_NOT_RUNNING |
drivers/gpu/drm/amd/amdgpu/../display/dc/dml2_0/dml2_wrapper_fpu.c dml_mode_support_wrapper() -> pack_and_call_dml_mode_support_ex()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dml2 | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy->ImmediateFlipRequirement | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy->MPCCombineUse | 2 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy->ODMUse | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.AllowForPStateChangeOrStutterInVBlankFinal | 0-1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.DRAMClockChangeRequirementFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.FCLKChangeRequirementFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.SynchronizeDRRDisplaysForUCLKPStateChangeFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.SynchronizeTimingsFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.USRRetrainingRequiredFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.UseOnlyMaxPrefetchModes | 1 |
| PARAM_VALUE | 0 | dml2->v20.scratch.cur_display_config->plane.BlendingAndTiming | 0-s32max |
| PARAM_VALUE | 0 | dml2->v20.scratch.cur_display_config->plane.UseMALLForPStateChange | 0,2-3 |
| PARAM_VALUE | 0 | dml2->v20.scratch.cur_display_config->plane.UseMALLForStaticScreen | 0,2 |
| PARAM_VALUE | 0 | dml2->v20.scratch.cur_display_config.num_surfaces | 1-s32max |
| PARAM_VALUE | 0 | dml2->v20.scratch.cur_display_config.num_timings | 1-s32max |
| PARAM_VALUE | 0 | *dml2->v20.dml_core_ctx.policy.ODMUse | 2,4 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.output.OutputBpp | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.output.PixelClockBackEnd | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.plane.HRatio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.plane.HRatioChroma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.plane.VRatio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.plane.VRatioChroma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.surface.DCCFractionOfZeroSizeRequestsChroma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.surface.DCCFractionOfZeroSizeRequestsLuma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.surface.DCCRateChroma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.surface.DCCRateLuma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.timing.PixelClock | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.writeback.WritebackHRatio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.writeback.WritebackVRatio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid | 0-1 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid | 0-1 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id | 0-4294967295 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid | 0-1 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.hpo_stream_to_link_encoder_mapping | s32min-s32max |
| PARAM_VALUE | 1 | display_cfg | 4096-ptr_max |
| PARAM_VALUE | 1 | display_cfg->num_surfaces | 1-s32max |
| PARAM_VALUE | 1 | display_cfg->num_timings | 1-s32max |
| PARAM_VALUE | 2 | evaluation_info | 4096-ptr_max |
| CAPPED_DATA | 0 | dml2->config.dcn_pipe_count | 1 |
| DATA_SOURCE | 0 | dml2 | $0 |
| DATA_SOURCE | 3 | validate_mode | $2 |
| MEM_ZERO | 1 | display_cfg |
drivers/gpu/drm/amd/amdgpu/../display/dc/dml2_0/dml2_wrapper_fpu.c dml_mode_support_wrapper() -> pack_and_call_dml_mode_support_ex()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dml2 | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ip.dispclk_ramp_margin_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ip.max_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ip.max_num_dpp | 0-s32max |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ip.max_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ip.writeback_max_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ip.writeback_max_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ip.writeback_min_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ip.writeback_min_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.BandwidthAvailableForImmediateFlip | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.DCFCLKDeepSleep | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Dcfclk | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Dispclk | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Dispclk_calculated | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.FractionOfUrgentBandwidth | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.FractionOfUrgentBandwidthImmediateFlip | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.GlobalDPPCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.MaxActiveFCLKChangeLatencySupported | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.StutterEfficiency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.StutterEfficiencyNotIncludingVBlank | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.StutterPeriod | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.StutterPeriodBestCase | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.TCalc | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.TotalDataReadBandwidth | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.TotalDataReadBandwidthNotIncludingMALLPrefetch | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.UrgentExtraLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.UrgentLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.UrgentLatencyWithUSRRetraining | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Watermark.DRAMClockChangeWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Watermark.FCLKChangeWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Watermark.StutterEnterPlusExitWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Watermark.StutterExitWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Watermark.USRRetrainingWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Watermark.UrgentWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Watermark.WritebackDRAMClockChangeWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Watermark.WritebackFCLKChangeWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Watermark.WritebackUrgentWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Watermark.Z8StutterEnterPlusExitWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Watermark.Z8StutterExitWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.WritebackDISPCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Z8StutterEfficiency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Z8StutterEfficiencyBestCase | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Z8StutterEfficiencyNotIncludingVBlank | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Z8StutterEfficiencyNotIncludingVBlankBestCase | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.non_urgent_total_dcn_read_bw_with_flip | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.total_dcn_read_bw_with_flip | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.total_dcn_read_bw_with_flip_no_urgent_burst | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.total_dcn_read_bw_with_flip_not_including_MALL_prefetch | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.BandwidthAvailableForImmediateFlip | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.DCFCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.DRAMSpeed | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.ExtraLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.FabricClock | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.GlobalDPPCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.MaximumSwathWidthInLineBufferChroma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.MaximumSwathWidthInLineBufferLuma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.ReturnBW | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.ReturnDRAMBW | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.SOCCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.TWait | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.TimeCalc | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.UrgLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.WritebackRequiredDISPCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.cache_display_cfg.clk_overrides.dcfclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.cache_display_cfg.clk_overrides.dispclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.cache_display_cfg.hw.DLGRefClkFreqMHz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.ip.dispclk_ramp_margin_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.ip.max_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.ip.max_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.ip.writeback_max_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.ip.writeback_max_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.ip.writeback_min_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.ip.writeback_min_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.dcfclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.dispclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.dppclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.dram_clock_change_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.dram_speed_mts | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.dscclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.dtbclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.fabricclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.fclk_change_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.g6_temp_read_blackout_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.phyclk_d18_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.phyclk_d32_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.phyclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.socclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.sr_enter_plus_exit_time_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.sr_enter_plus_exit_z8_time_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.sr_exit_time_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.sr_exit_z8_time_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.urgent_latency_pixel_data_only_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.urgent_latency_pixel_mixed_with_vm_data_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.urgent_latency_vm_data_only_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.usr_retraining_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.writeback_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.amclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.dcn_downspread_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.dispclk_dppclk_vco_speed_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.dml_dcn401_soc_qos_params.umc_average_latency_margin | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.dml_dcn401_soc_qos_params.umc_max_latency_margin | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.dprefclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.max_avg_dram_bw_use_normal_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.max_avg_dram_bw_use_normal_strobe_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.max_avg_fabric_bw_use_normal_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.max_avg_sdp_bw_use_normal_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.pcierefclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.pct_ideal_dram_bw_after_urgent_pixel_and_vm | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.pct_ideal_dram_bw_after_urgent_pixel_only | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.pct_ideal_dram_bw_after_urgent_strobe | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.pct_ideal_dram_bw_after_urgent_vm_only | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.pct_ideal_fabric_bw_after_urgent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.pct_ideal_sdp_bw_after_urgent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.phy_downspread_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.refclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.smn_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.svp_prefetch_max_avg_dram_bw_use_normal_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.svp_prefetch_max_avg_fabric_bw_use_normal_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.svp_prefetch_max_avg_sdp_bw_use_normal_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.svp_prefetch_pct_ideal_dram_bw_after_urgent_vm_only | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.svp_prefetch_pct_ideal_fabric_bw_after_urgent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.svp_prefetch_pct_ideal_sdp_bw_after_urgent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.xtalclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.dcfclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.dispclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.dppclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.dram_clock_change_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.dram_speed_mts | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.dscclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.dtbclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.fabricclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.fclk_change_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.g6_temp_read_blackout_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.phyclk_d18_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.phyclk_d32_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.phyclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.socclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.sr_enter_plus_exit_time_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.sr_enter_plus_exit_z8_time_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.sr_exit_time_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.sr_exit_z8_time_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.urgent_latency_pixel_data_only_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.urgent_latency_pixel_mixed_with_vm_data_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.urgent_latency_vm_data_only_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.usr_retraining_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.writeback_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy->ImmediateFlipRequirement | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy->MPCCombineUse | 2 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy->ODMUse | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.LineTime | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Lsw_oto | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.PrefetchBandwidth1 | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.PrefetchBandwidth2 | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.PrefetchBandwidth3 | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.PrefetchBandwidth4 | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tdmbf | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tdmec | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tdmsks | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tpre_rounded | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tr0_equ | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tr0_oto | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tr0_oto_lines | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tr0_trips | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tr0_trips_rounded | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tsw_est1 | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tsw_est3 | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tvm_equ | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tvm_oto | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tvm_oto_lines | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tvm_trips | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tvm_trips_rounded | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.bytes_pp | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.dep_bytes | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.dst_y_prefetch_equ | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.dst_y_prefetch_oto | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.max_Tsw | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.min_Lsw_oto | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.prefetch_bw_equ | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.prefetch_bw_oto | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.prefetch_bw_pr | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.prefetch_sw_bytes | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.trip_to_mem | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_params.DPPCLKDelaySCL | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_params.TCalc | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_params.TWait | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_params.UrgentExtraLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_params.UrgentLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculateStutterEfficiency_params.DCFCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculateStutterEfficiency_params.ReturnBW | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculateStutterEfficiency_params.SRExitTime | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculateStutterEfficiency_params.SRExitZ8Time | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_locals.DPTEBandwidth | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_locals.ExtraLatencyCycles | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_locals.MinimumTWait | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_locals.MinimumTvmPlus2Tr0 | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_locals.NormalEfficiency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_params.DCFCLKPerState | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_params.DRAMClockChangeLatencyFinal | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_params.FCLKChangeLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_params.SREnterPlusExitTime | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_params.UrgLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_programming_locals.LSetup | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_programming_locals.TotalWRBandwidth | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_programming_locals.Tvstartup_margin | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_programming_locals.VMDataOnlyReturnBW | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_programming_locals.WRBandwidth | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_programming_locals.dlg_vblank_start | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_programming_locals.myPipe.Dispclk | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_programming_locals.myPipe.Dppclk | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_programming_locals.myPipe.PixelClock | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_programming_locals.myPipe.VRatio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_support_locals.myPipe.DCFClkDeepSleep | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_support_locals.myPipe.Dispclk | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_support_locals.myPipe.Dppclk | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_support_locals.myPipe.PixelClock | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_support_locals.myPipe.VRatio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_support_locals.myPipe.VRatioChroma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.amclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.dcn_downspread_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.dispclk_dppclk_vco_speed_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.dml_dcn401_soc_qos_params.umc_average_latency_margin | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.dml_dcn401_soc_qos_params.umc_max_latency_margin | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.dprefclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.max_avg_dram_bw_use_normal_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.max_avg_dram_bw_use_normal_strobe_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.max_avg_fabric_bw_use_normal_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.max_avg_sdp_bw_use_normal_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.pcierefclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.pct_ideal_dram_bw_after_urgent_pixel_and_vm | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.pct_ideal_dram_bw_after_urgent_pixel_only | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.pct_ideal_dram_bw_after_urgent_strobe | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.pct_ideal_dram_bw_after_urgent_vm_only | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.pct_ideal_fabric_bw_after_urgent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.pct_ideal_sdp_bw_after_urgent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.phy_downspread_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.refclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.smn_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.svp_prefetch_max_avg_dram_bw_use_normal_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.svp_prefetch_max_avg_fabric_bw_use_normal_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.svp_prefetch_max_avg_sdp_bw_use_normal_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.svp_prefetch_pct_ideal_dram_bw_after_urgent_pixel_only | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.svp_prefetch_pct_ideal_dram_bw_after_urgent_vm_only | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.svp_prefetch_pct_ideal_fabric_bw_after_urgent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.svp_prefetch_pct_ideal_sdp_bw_after_urgent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.xtalclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.cur_display_config->plane.BlendingAndTiming | 0-s32max |
| PARAM_VALUE | 0 | dml2->v20.scratch.cur_display_config->plane.UseMALLForPStateChange | 0,2-3 |
| PARAM_VALUE | 0 | dml2->v20.scratch.cur_display_config->plane.UseMALLForStaticScreen | 0,2 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.in_display_cfg | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.in_display_cfg->num_surfaces | 1-s32max |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.in_display_cfg->num_timings | 1-s32max |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ip.dispclk_ramp_margin_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ip.max_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ip.max_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ip.writeback_max_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ip.writeback_max_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ip.writeback_min_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ip.writeback_min_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.DCFCLKDeepSleep | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.Dcfclk | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.Dispclk | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.Dispclk_calculated | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.FractionOfUrgentBandwidth | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.GlobalDPPCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.StutterEfficiency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.StutterPeriod | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.StutterPeriodBestCase | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.TCalc | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.TotalDataReadBandwidth | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.UrgentExtraLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.UrgentLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.UrgentLatencyWithUSRRetraining | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.Watermark.FCLKChangeWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.Watermark.StutterExitWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.Watermark.UrgentWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.WritebackDISPCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.Z8StutterEfficiency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.Z8StutterEfficiencyBestCase | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.total_dcn_read_bw_with_flip | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.DCFCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.DRAMSpeed | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.ExtraLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.FabricClock | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.GlobalDPPCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.ReturnBW | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.ReturnDRAMBW | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.SOCCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.TWait | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.TimeCalc | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.UrgLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.WritebackRequiredDISPCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.ip.dispclk_ramp_margin_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.ip.max_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.ip.max_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.ip.writeback_max_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.ip.writeback_max_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.ip.writeback_min_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.ip.writeback_min_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.dcfclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.dispclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.dppclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.dram_speed_mts | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.dscclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.dtbclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.fabricclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.phyclk_d18_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.phyclk_d32_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.phyclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.socclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.sr_exit_time_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.sr_exit_z8_time_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.writeback_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.soc.amclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.soc.dcn_downspread_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.soc.dprefclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.soc.pcierefclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.soc.phy_downspread_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.soc.refclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.soc.smn_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.soc.xtalclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.dcfclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.dispclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.dppclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.dram_speed_mts | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.dscclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.dtbclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.fabricclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.fclk_change_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.g6_temp_read_blackout_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.phyclk_d18_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.phyclk_d32_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.phyclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.socclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.sr_exit_time_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.sr_exit_z8_time_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.usr_retraining_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.writeback_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->soc.amclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->soc.dcn_downspread_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->soc.dispclk_dppclk_vco_speed_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->soc.dprefclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->soc.pcierefclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->soc.pct_ideal_sdp_bw_after_urgent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->soc.phy_downspread_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->soc.refclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->soc.smn_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->soc.xtalclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.out_evaluation_info | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.config | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.cur_display_config | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.cur_mode_support_info | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.cur_policy | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ip.max_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ip.max_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->mp.DCFCLKDeepSleep | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->mp.Dcfclk | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->mp.Dispclk | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->mp.GlobalDPPCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->mp.StutterEfficiency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->mp.StutterPeriod | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->mp.TCalc | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->mp.UrgentLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->mp.WritebackDISPCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.DCFCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.DRAMSpeed | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.ExtraLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.FabricClock | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.GlobalDPPCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.ReturnBW | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.ReturnDRAMBW | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.SOCCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.TWait | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.TimeCalc | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.UrgLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.ip.max_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.ip.max_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.soc.amclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.soc.dprefclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.soc.refclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.soc.xtalclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.state.dcfclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.state.dispclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.state.dppclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.state.dscclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.state.dtbclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.state.phyclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.state.socclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->soc.amclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->soc.dprefclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->soc.pcierefclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->soc.refclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->soc.smn_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->soc.xtalclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.ip_params | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.ip_params->max_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.ip_params->max_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.new_display_config | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.new_policy | 4096-ptr_max |
| PARAM_VALUE | 0 | *dml2->v20.dml_core_ctx.policy.ODMUse | 2,4 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.output.OutputBpp | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.output.PixelClockBackEnd | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.plane.HRatio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.plane.HRatioChroma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.plane.VRatio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.plane.VRatioChroma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.surface.DCCFractionOfZeroSizeRequestsChroma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.surface.DCCFractionOfZeroSizeRequestsLuma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.surface.DCCRateChroma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.surface.DCCRateLuma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.timing.PixelClock | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.writeback.WritebackHRatio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.writeback.WritebackVRatio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid | 0-1 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid | 0-1 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id | 0-4294967295 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid | 0-1 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.hpo_stream_to_link_encoder_mapping | s32min-s32max |
| PARAM_VALUE | 1 | display_cfg | 4096-ptr_max |
| PARAM_VALUE | 2 | evaluation_info | 4096-ptr_max |
| PARAM_VALUE | 2 | evaluation_info->ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified | 0 |
| CAPPED_DATA | 0 | dml2->config.dcn_pipe_count | 1 |
| DATA_SOURCE | 0 | dml2 | $0 |
| DATA_SOURCE | 3 | validate_mode | $2 |
| MEM_ZERO | 2 | evaluation_info |
drivers/gpu/drm/amd/amdgpu/../display/dc/dml2_0/dml2_wrapper_fpu.c dml_mode_support_wrapper() -> pack_and_call_dml_mode_support_ex()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dml2 | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ip.dispclk_ramp_margin_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ip.max_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ip.max_num_dpp | 0-s32max |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ip.max_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ip.writeback_max_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ip.writeback_max_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ip.writeback_min_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ip.writeback_min_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.BandwidthAvailableForImmediateFlip | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.DCFCLKDeepSleep | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Dcfclk | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Dispclk | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Dispclk_calculated | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.FractionOfUrgentBandwidth | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.FractionOfUrgentBandwidthImmediateFlip | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.GlobalDPPCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.MaxActiveFCLKChangeLatencySupported | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.StutterEfficiency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.StutterEfficiencyNotIncludingVBlank | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.StutterPeriod | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.StutterPeriodBestCase | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.TCalc | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.TotalDataReadBandwidth | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.TotalDataReadBandwidthNotIncludingMALLPrefetch | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.UrgentExtraLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.UrgentLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.UrgentLatencyWithUSRRetraining | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Watermark.DRAMClockChangeWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Watermark.FCLKChangeWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Watermark.StutterEnterPlusExitWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Watermark.StutterExitWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Watermark.USRRetrainingWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Watermark.UrgentWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Watermark.WritebackDRAMClockChangeWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Watermark.WritebackFCLKChangeWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Watermark.WritebackUrgentWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Watermark.Z8StutterEnterPlusExitWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Watermark.Z8StutterExitWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.WritebackDISPCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Z8StutterEfficiency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Z8StutterEfficiencyBestCase | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Z8StutterEfficiencyNotIncludingVBlank | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.Z8StutterEfficiencyNotIncludingVBlankBestCase | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.non_urgent_total_dcn_read_bw_with_flip | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.total_dcn_read_bw_with_flip | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.total_dcn_read_bw_with_flip_no_urgent_burst | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.mp.total_dcn_read_bw_with_flip_not_including_MALL_prefetch | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.BandwidthAvailableForImmediateFlip | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.DCFCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.DRAMSpeed | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.ExtraLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.FabricClock | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.GlobalDPPCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.MaximumSwathWidthInLineBufferChroma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.MaximumSwathWidthInLineBufferLuma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.ReturnBW | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.ReturnDRAMBW | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.SOCCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.TWait | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.TimeCalc | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.UrgLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.WritebackRequiredDISPCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.cache_display_cfg.clk_overrides.dcfclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.cache_display_cfg.clk_overrides.dispclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.cache_display_cfg.hw.DLGRefClkFreqMHz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.ip.dispclk_ramp_margin_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.ip.max_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.ip.max_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.ip.writeback_max_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.ip.writeback_max_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.ip.writeback_min_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.ip.writeback_min_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.dcfclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.dispclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.dppclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.dram_clock_change_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.dram_speed_mts | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.dscclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.dtbclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.fabricclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.fclk_change_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.g6_temp_read_blackout_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.phyclk_d18_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.phyclk_d32_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.phyclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.socclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.sr_enter_plus_exit_time_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.sr_enter_plus_exit_z8_time_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.sr_exit_time_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.sr_exit_z8_time_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.urgent_latency_pixel_data_only_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.urgent_latency_pixel_mixed_with_vm_data_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.urgent_latency_vm_data_only_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.usr_retraining_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.max_state.writeback_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.amclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.dcn_downspread_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.dispclk_dppclk_vco_speed_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.dml_dcn401_soc_qos_params.umc_average_latency_margin | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.dml_dcn401_soc_qos_params.umc_max_latency_margin | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.dprefclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.max_avg_dram_bw_use_normal_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.max_avg_dram_bw_use_normal_strobe_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.max_avg_fabric_bw_use_normal_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.max_avg_sdp_bw_use_normal_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.pcierefclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.pct_ideal_dram_bw_after_urgent_pixel_and_vm | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.pct_ideal_dram_bw_after_urgent_pixel_only | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.pct_ideal_dram_bw_after_urgent_strobe | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.pct_ideal_dram_bw_after_urgent_vm_only | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.pct_ideal_fabric_bw_after_urgent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.pct_ideal_sdp_bw_after_urgent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.phy_downspread_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.refclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.smn_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.svp_prefetch_max_avg_dram_bw_use_normal_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.svp_prefetch_max_avg_fabric_bw_use_normal_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.svp_prefetch_max_avg_sdp_bw_use_normal_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.svp_prefetch_pct_ideal_dram_bw_after_urgent_vm_only | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.svp_prefetch_pct_ideal_fabric_bw_after_urgent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.svp_prefetch_pct_ideal_sdp_bw_after_urgent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.soc.xtalclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.dcfclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.dispclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.dppclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.dram_clock_change_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.dram_speed_mts | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.dscclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.dtbclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.fabricclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.fclk_change_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.g6_temp_read_blackout_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.phyclk_d18_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.phyclk_d32_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.phyclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.socclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.sr_enter_plus_exit_time_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.sr_enter_plus_exit_z8_time_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.sr_exit_time_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.sr_exit_z8_time_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.urgent_latency_pixel_data_only_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.urgent_latency_pixel_mixed_with_vm_data_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.urgent_latency_vm_data_only_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.usr_retraining_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.ms.state.writeback_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy->ImmediateFlipRequirement | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy->MPCCombineUse | 2 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy->ODMUse | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.LineTime | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Lsw_oto | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.PrefetchBandwidth1 | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.PrefetchBandwidth2 | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.PrefetchBandwidth3 | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.PrefetchBandwidth4 | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tdmbf | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tdmec | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tdmsks | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tpre_rounded | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tr0_equ | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tr0_oto | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tr0_oto_lines | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tr0_trips | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tr0_trips_rounded | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tsw_est1 | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tsw_est3 | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tvm_equ | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tvm_oto | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tvm_oto_lines | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tvm_trips | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tvm_trips_rounded | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.bytes_pp | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.dep_bytes | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.dst_y_prefetch_equ | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.dst_y_prefetch_oto | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.max_Tsw | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.min_Lsw_oto | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.prefetch_bw_equ | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.prefetch_bw_oto | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.prefetch_bw_pr | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.prefetch_sw_bytes | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.trip_to_mem | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_params.DPPCLKDelaySCL | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_params.TCalc | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_params.TWait | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_params.UrgentExtraLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_params.UrgentLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculateStutterEfficiency_params.DCFCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculateStutterEfficiency_params.ReturnBW | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculateStutterEfficiency_params.SRExitTime | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.CalculateStutterEfficiency_params.SRExitZ8Time | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_locals.DPTEBandwidth | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_locals.ExtraLatencyCycles | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_locals.MinimumTWait | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_locals.MinimumTvmPlus2Tr0 | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_locals.NormalEfficiency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_params.DCFCLKPerState | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_params.DRAMClockChangeLatencyFinal | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_params.FCLKChangeLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_params.SREnterPlusExitTime | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_params.UrgLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_programming_locals.LSetup | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_programming_locals.TotalWRBandwidth | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_programming_locals.Tvstartup_margin | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_programming_locals.VMDataOnlyReturnBW | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_programming_locals.WRBandwidth | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_programming_locals.dlg_vblank_start | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_programming_locals.myPipe.Dispclk | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_programming_locals.myPipe.Dppclk | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_programming_locals.myPipe.PixelClock | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_programming_locals.myPipe.VRatio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_support_locals.myPipe.DCFClkDeepSleep | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_support_locals.myPipe.Dispclk | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_support_locals.myPipe.Dppclk | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_support_locals.myPipe.PixelClock | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_support_locals.myPipe.VRatio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.scratch.dml_core_mode_support_locals.myPipe.VRatioChroma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.amclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.dcn_downspread_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.dispclk_dppclk_vco_speed_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.dml_dcn401_soc_qos_params.umc_average_latency_margin | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.dml_dcn401_soc_qos_params.umc_max_latency_margin | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.dprefclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.max_avg_dram_bw_use_normal_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.max_avg_dram_bw_use_normal_strobe_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.max_avg_fabric_bw_use_normal_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.max_avg_sdp_bw_use_normal_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.pcierefclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.pct_ideal_dram_bw_after_urgent_pixel_and_vm | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.pct_ideal_dram_bw_after_urgent_pixel_only | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.pct_ideal_dram_bw_after_urgent_strobe | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.pct_ideal_dram_bw_after_urgent_vm_only | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.pct_ideal_fabric_bw_after_urgent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.pct_ideal_sdp_bw_after_urgent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.phy_downspread_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.refclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.smn_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.svp_prefetch_max_avg_dram_bw_use_normal_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.svp_prefetch_max_avg_fabric_bw_use_normal_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.svp_prefetch_max_avg_sdp_bw_use_normal_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.svp_prefetch_pct_ideal_dram_bw_after_urgent_pixel_only | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.svp_prefetch_pct_ideal_dram_bw_after_urgent_vm_only | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.svp_prefetch_pct_ideal_fabric_bw_after_urgent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.svp_prefetch_pct_ideal_sdp_bw_after_urgent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.soc.xtalclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.cur_display_config->plane.BlendingAndTiming | 0-s32max |
| PARAM_VALUE | 0 | dml2->v20.scratch.cur_display_config->plane.UseMALLForPStateChange | 0,2-3 |
| PARAM_VALUE | 0 | dml2->v20.scratch.cur_display_config->plane.UseMALLForStaticScreen | 0,2 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.in_display_cfg | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.in_display_cfg->num_surfaces | 1-s32max |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.in_display_cfg->num_timings | 1-s32max |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ip.dispclk_ramp_margin_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ip.max_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ip.max_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ip.writeback_max_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ip.writeback_max_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ip.writeback_min_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ip.writeback_min_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.DCFCLKDeepSleep | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.Dcfclk | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.Dispclk | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.Dispclk_calculated | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.FractionOfUrgentBandwidth | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.GlobalDPPCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.StutterEfficiency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.StutterPeriod | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.StutterPeriodBestCase | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.TCalc | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.TotalDataReadBandwidth | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.UrgentExtraLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.UrgentLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.UrgentLatencyWithUSRRetraining | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.Watermark.FCLKChangeWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.Watermark.StutterExitWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.Watermark.UrgentWatermark | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.WritebackDISPCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.Z8StutterEfficiency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.Z8StutterEfficiencyBestCase | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->mp.total_dcn_read_bw_with_flip | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.DCFCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.DRAMSpeed | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.ExtraLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.FabricClock | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.GlobalDPPCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.ReturnBW | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.ReturnDRAMBW | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.SOCCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.TWait | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.TimeCalc | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.UrgLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.WritebackRequiredDISPCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.ip.dispclk_ramp_margin_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.ip.max_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.ip.max_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.ip.writeback_max_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.ip.writeback_max_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.ip.writeback_min_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.ip.writeback_min_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.dcfclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.dispclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.dppclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.dram_speed_mts | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.dscclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.dtbclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.fabricclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.phyclk_d18_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.phyclk_d32_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.phyclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.socclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.sr_exit_time_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.sr_exit_z8_time_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.max_state.writeback_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.soc.amclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.soc.dcn_downspread_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.soc.dprefclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.soc.pcierefclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.soc.phy_downspread_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.soc.refclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.soc.smn_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.soc.xtalclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.dcfclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.dispclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.dppclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.dram_speed_mts | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.dscclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.dtbclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.fabricclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.fclk_change_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.g6_temp_read_blackout_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.phyclk_d18_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.phyclk_d32_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.phyclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.socclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.sr_exit_time_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.sr_exit_z8_time_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.usr_retraining_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->ms.state.writeback_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->soc.amclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->soc.dcn_downspread_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->soc.dispclk_dppclk_vco_speed_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->soc.dprefclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->soc.pcierefclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->soc.pct_ideal_sdp_bw_after_urgent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->soc.phy_downspread_percent | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->soc.refclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->soc.smn_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.mode_lib->soc.xtalclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.mode_support_params.out_evaluation_info | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.config | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.cur_display_config | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.cur_mode_support_info | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.cur_policy | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ip.max_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ip.max_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->mp.DCFCLKDeepSleep | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->mp.Dcfclk | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->mp.Dispclk | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->mp.GlobalDPPCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->mp.StutterEfficiency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->mp.StutterPeriod | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->mp.TCalc | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->mp.UrgentLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->mp.WritebackDISPCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.DCFCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.DRAMSpeed | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.ExtraLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.FabricClock | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.GlobalDPPCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.ReturnBW | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.ReturnDRAMBW | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.SOCCLK | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.TWait | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.TimeCalc | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.UrgLatency | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.ip.max_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.ip.max_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.soc.amclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.soc.dprefclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.soc.refclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.soc.xtalclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.state.dcfclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.state.dispclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.state.dppclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.state.dscclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.state.dtbclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.state.phyclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->ms.state.socclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->soc.amclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->soc.dprefclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->soc.pcierefclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->soc.refclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->soc.smn_latency_us | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.dml_core_ctx->soc.xtalclk_mhz | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.ip_params | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.ip_params->max_hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.ip_params->max_vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.new_display_config | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.scratch.optimize_configuration_params.new_policy | 4096-ptr_max |
| PARAM_VALUE | 0 | *dml2->v20.dml_core_ctx.policy.ODMUse | 2,4 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.output.OutputBpp | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.output.PixelClockBackEnd | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.plane.HRatio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.plane.HRatioChroma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.plane.VRatio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.plane.VRatioChroma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.surface.DCCFractionOfZeroSizeRequestsChroma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.surface.DCCFractionOfZeroSizeRequestsLuma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.surface.DCCRateChroma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.surface.DCCRateLuma | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.timing.PixelClock | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.writeback.WritebackHRatio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch->cur_display_config.writeback.WritebackVRatio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid | 0-1 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid | 0-1 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id | 0-4294967295 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid | 0-1 |
| PARAM_VALUE | 0 | *dml2->v20.scratch.hpo_stream_to_link_encoder_mapping | s32min-s32max |
| PARAM_VALUE | 1 | display_cfg | 4096-ptr_max |
| PARAM_VALUE | 2 | evaluation_info | 4096-ptr_max |
| PARAM_VALUE | 2 | evaluation_info->ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified | 0 |
| CAPPED_DATA | 0 | dml2->config.dcn_pipe_count | 1 |
| DATA_SOURCE | 0 | dml2 | $0 |
| DATA_SOURCE | 3 | validate_mode | $2 |
| MEM_ZERO | 1 | display_cfg | |
| MEM_ZERO | 2 | evaluation_info |