Defined in 1 files as a member:

Defined in 1 files as a function:

Referenced in 10 files:

Smatch caller information:

drivers/net/wireless/intel/iwlwifi/pcie/gen1_2/trans.c iwl_pcie_init_msix_handler() -> queue_name()

Type Parameter Key Value
PARAM_VALUE 0 dev 4096-ptr_max
PARAM_VALUE 1 trans_p 4096-ptr_max
PARAM_VALUE 1 trans_p->alloc_vecs 1-u32max
PARAM_VALUE 1 trans_p->debug_rfkill (-1)
PARAM_VALUE 1 trans_p->fh_mask 0
PARAM_VALUE 1 trans_p->fw_reset_waitq.head.next 4096-ptr_max
PARAM_VALUE 1 trans_p->fw_reset_waitq.head.next->next 4096-ptr_max
PARAM_VALUE 1 trans_p->fw_reset_waitq.head.prev 4096-ptr_max
PARAM_VALUE 1 trans_p->fw_reset_waitq.head.prev->next 4096-ptr_max
PARAM_VALUE 1 trans_p->fw_reset_waitq.head.prev->prev 4096-ptr_max
PARAM_VALUE 1 trans_p->hw_base 4096-ptr_max
PARAM_VALUE 1 trans_p->hw_mask 0
PARAM_VALUE 1 trans_p->imr_waitq.head.next 4096-ptr_max
PARAM_VALUE 1 trans_p->imr_waitq.head.next->next 4096-ptr_max
PARAM_VALUE 1 trans_p->imr_waitq.head.prev 4096-ptr_max
PARAM_VALUE 1 trans_p->imr_waitq.head.prev->next 4096-ptr_max
PARAM_VALUE 1 trans_p->imr_waitq.head.prev->prev 4096-ptr_max
PARAM_VALUE 1 trans_p->msix_enabled 1
PARAM_VALUE 1 trans_p->msix_entries->vector 0-4294967295
PARAM_VALUE 1 trans_p->mutex.dep_map->name 0-255
PARAM_VALUE 1 trans_p->mutex.first_waiter 0
PARAM_VALUE 1 trans_p->mutex.magic 4096-ptr_max
PARAM_VALUE 1 trans_p->mutex.osq.tail.counter 0
PARAM_VALUE 1 trans_p->mutex.owner.counter 0
PARAM_VALUE 1 trans_p->napi_dev 1-u64max
PARAM_VALUE 1 trans_p->opmode_down 1
PARAM_VALUE 1 trans_p->pci_dev 4096-ptr_max
PARAM_VALUE 1 trans_p->pci_dev->bus 4096-ptr_max
PARAM_VALUE 1 trans_p->pci_dev->dev.devres_head.prev 4096-ptr_max
PARAM_VALUE 1 trans_p->pci_dev->dev.dma_mask 4096-ptr_max
PARAM_VALUE 1 trans_p->pci_dev->driver 4096-ptr_max
PARAM_VALUE 1 trans_p->pci_dev->error_state 0-2,4-u32max
PARAM_VALUE 1 trans_p->pci_dev->is_busmaster 1
PARAM_VALUE 1 trans_p->pci_dev->is_managed 1
PARAM_VALUE 1 trans_p->pci_dev->pcie_cap 0-1
PARAM_VALUE 1 trans_p->rba.alloc_wq 4096-ptr_max
PARAM_VALUE 1 trans_p->supported_dma_mask 2047,4095
PARAM_VALUE 1 trans_p->sx_waitq.head.next 4096-ptr_max
PARAM_VALUE 1 trans_p->sx_waitq.head.next->next 4096-ptr_max
PARAM_VALUE 1 trans_p->sx_waitq.head.prev 4096-ptr_max
PARAM_VALUE 1 trans_p->sx_waitq.head.prev->next 4096-ptr_max
PARAM_VALUE 1 trans_p->sx_waitq.head.prev->prev 4096-ptr_max
PARAM_VALUE 1 trans_p->trans 4096-ptr_max
PARAM_VALUE 1 trans_p->trans->dev 4096-ptr_max
PARAM_VALUE 1 trans_p->trans->mac_cfg 4096-ptr_max
PARAM_VALUE 1 trans_p->txqs.bc_tbl_size 640,2048,8192
PARAM_VALUE 1 trans_p->txqs.tfd.addr_size 36,64
PARAM_VALUE 1 trans_p->txqs.tfd.max_tbs 20,25
PARAM_VALUE 1 trans_p->txqs.tfd.size 128,256
PARAM_VALUE 1 trans_p->txqs.tso_hdr_page 4096-ptr_max
PARAM_VALUE 1 trans_p->ucode_write_waitq.head.next 4096-ptr_max
PARAM_VALUE 1 trans_p->ucode_write_waitq.head.next->next 4096-ptr_max
PARAM_VALUE 1 trans_p->ucode_write_waitq.head.prev 4096-ptr_max
PARAM_VALUE 1 trans_p->ucode_write_waitq.head.prev->next 4096-ptr_max
PARAM_VALUE 1 trans_p->ucode_write_waitq.head.prev->prev 4096-ptr_max
PARAM_VALUE 1 trans_p->wait_command_queue.head.next 4096-ptr_max
PARAM_VALUE 1 trans_p->wait_command_queue.head.next->next 4096-ptr_max
PARAM_VALUE 1 trans_p->wait_command_queue.head.prev 4096-ptr_max
PARAM_VALUE 1 trans_p->wait_command_queue.head.prev->next 4096-ptr_max
PARAM_VALUE 1 trans_p->wait_command_queue.head.prev->prev 4096-ptr_max
PARAM_VALUE 1 *trans_p->napi_dev->priv->supported_dma_mask 2047,4095
PARAM_VALUE 1 *trans_p->napi_dev->priv->txqs.bc_tbl_size 640,2048,8192
PARAM_VALUE 1 *trans_p->napi_dev->priv->txqs.tfd.addr_size 36,64
PARAM_VALUE 1 *trans_p->napi_dev->priv->txqs.tfd.max_tbs 20,25
PARAM_VALUE 1 *trans_p->napi_dev->priv->txqs.tfd.size 128,256
PARAM_VALUE 2 i 0-s32max
BUF_SIZE 1 trans_p 25776
BUF_SIZE 1 trans_p->pci_dev (-1),1-s32max
BUF_SIZE 1 trans_p->rba.alloc_wq (-1),512,528-8720
BUF_SIZE 1 trans_p->trans 29232
BUF_SIZE 1 trans_p->txqs.tso_hdr_page 16
CAPPED_DATA 1 trans_p->txqs.bc_tbl_size 1
CAPPED_DATA 1 trans_p->txqs.tfd.addr_size 1
CAPPED_DATA 2 i 1
DATA_SOURCE 1 trans_p $1
FUZZY_MAX 1 trans_p->supported_dma_mask 4095
FUZZY_MAX 1 trans_p->txqs.bc_tbl_size 8192
FUZZY_MAX 1 trans_p->txqs.tfd.addr_size 64
FUZZY_MAX 1 trans_p->txqs.tfd.max_tbs 25
FUZZY_MAX 1 trans_p->txqs.tfd.size 256
FUZZY_MAX 2 i 0
PARAM_COMPARE 2 i < $1->alloc_vecs
BIT_INFO 1 trans_p->supported_dma_mask 0x7ff,0xffffffffffffffff
BIT_INFO 1 trans_p->txqs.tfd.addr_size 0x0,0x64
BIT_INFO 1 trans_p->txqs.tfd.max_tbs 0x10,0xffffffffffffffff
BIT_INFO 1 trans_p->txqs.tfd.size 0x0,0x180
HARD_MAX 1 trans_p->supported_dma_mask 4095
HARD_MAX 1 trans_p->txqs.bc_tbl_size 8192
HARD_MAX 1 trans_p->txqs.tfd.addr_size 64
HARD_MAX 1 trans_p->txqs.tfd.max_tbs 25
HARD_MAX 1 trans_p->txqs.tfd.size 256
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 1 trans_p->pci_dev->acs_capabilities 0-u16max
HOST_DATA 1 trans_p->pci_dev->class 0-16777215
HOST_DATA 1 trans_p->pci_dev->current_state 0-3[c]
HOST_DATA 1 trans_p->pci_dev->devcap 0-u32max
HOST_DATA 1 trans_p->pci_dev->devfn 0-503[c]
HOST_DATA 1 trans_p->pci_dev->device 0-u16max
HOST_DATA 1 trans_p->pci_dev->eetlp_prefix_max 0-7[c]
HOST_DATA 1 trans_p->pci_dev->fm_enabled 0-1[c]
HOST_DATA 1 trans_p->pci_dev->hdr_type 0-255[c]
HOST_DATA 1 trans_p->pci_dev->ide_cfg 0-1[c]
HOST_DATA 1 trans_p->pci_dev->ide_tee_limit 0-1[c]
HOST_DATA 1 trans_p->pci_dev->irq 0-255
HOST_DATA 1 trans_p->pci_dev->is_cxl 0-1
HOST_DATA 1 trans_p->pci_dev->multifunction 0-1[c]
HOST_DATA 1 trans_p->pci_dev->nr_ide_mem 0-255[c]
HOST_DATA 1 trans_p->pci_dev->pcie_flags_reg 0-u16max
HOST_DATA 1 trans_p->pci_dev->pcie_mpss 0-7[c]
HOST_DATA 1 trans_p->pci_dev->pin 0
HOST_DATA 1 trans_p->pci_dev->pme_support 0-31[c]
HOST_DATA 1 trans_p->pci_dev->ptm_granularity 0-255[c]
HOST_DATA 1 trans_p->pci_dev->revision 0-255
HOST_DATA 1 trans_p->pci_dev->subsystem_device 0-u16max
HOST_DATA 1 trans_p->pci_dev->subsystem_vendor 0-u16max
HOST_DATA 1 trans_p->pci_dev->supported_speeds 0,2-254[c]
HOST_DATA 1 trans_p->pci_dev->transparent 0[c]
HOST_DATA 1 trans_p->pci_dev->vendor 0-u16max
HALF_LOCKED2 &pdev->dev.mutex
HALF_LOCKED2 &pool->lock