| PARAM_VALUE |
0 |
rdev |
4096-ptr_max |
| PARAM_VALUE |
0 |
rdev->asic |
4096-ptr_max |
| PARAM_VALUE |
0 |
rdev->asic->get_xclk |
4096-ptr_max |
| PARAM_VALUE |
0 |
rdev->family |
52-56 |
| PARAM_VALUE |
0 |
rdev->mman.bdev.pool.dev->iommu->attach_deferred |
0-1 |
| PARAM_VALUE |
0 |
rdev->mmio_idx_lock.rlock.dep_map->name |
0-255 |
| PARAM_VALUE |
0 |
rdev->mode_info.atom_context->fb_base |
0 |
| PARAM_VALUE |
0 |
rdev->mode_info.atom_context->io_mode |
0 |
| PARAM_VALUE |
0 |
rdev->mode_info.atom_context->mutex->first_waiter->task->blocked_lock.owner |
(-4611686018427387904)-4611686018427387903 |
| PARAM_VALUE |
0 |
rdev->mode_info.atom_context->reg_block |
0 |
| PARAM_VALUE |
0 |
rdev->mode_info.atom_context->scratch_mutex.dep_map->name |
0-255 |
| PARAM_VALUE |
0 |
rdev->mode_info.atom_context->scratch_mutex.first_waiter->list.prev->next |
5159360019465732096 |
| PARAM_VALUE |
0 |
rdev->mode_info.atom_context->scratch_mutex.first_waiter->list.prev->prev |
5159360019465732096 |
| PARAM_VALUE |
0 |
rdev->mode_info.atom_context->scratch_mutex.osq.tail.counter |
0-s32max |
| PARAM_VALUE |
0 |
rdev->pcie_idx_lock.rlock.dep_map->name |
0-255 |
| PARAM_VALUE |
0 |
rdev->pciep_idx_lock.rlock.dep_map->name |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.boot_ps |
4096-ptr_max |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv |
4096-ptr_max |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->arb_table_start |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->bsp |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->bsu |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->cac_table_start |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->dsp |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->dte_table_start |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->fan_table_start |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->mc_reg_table_start |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->mvdd_control |
0-1 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->papm_cfg_table_start |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->papm_parm.NearTDPLimitPAPM |
4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->papm_parm.NearTDPLimitTherm |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->papm_parm.PlatformPowerLimit |
4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->papm_parm.dGPU_T_Hysteresis |
5 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->papm_parm.dGPU_T_Limit |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->papm_parm.dGPU_T_Warning |
95 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->pbsp |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->pbsu |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->psp |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ACPIState.flags |
0,2-254 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ACPIState.level.SQPowerThrottle |
0,1073692671 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ACPIState.level.SQPowerThrottle_2 |
0,2080325631 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ACPIState.level.aT |
0,u16max |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ACPIState.level.mcFlags |
0,3 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ACPIState.level.mclk.vMCLK_PWRMGT_CNTL |
0,196608-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_2 |
0,4-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ACPIState.level.strobeMode |
0-31 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ACPIState.levelCount |
0-1 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.flags |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.ACIndex |
0-1 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.MaxPoweredUpCU |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.SQPowerThrottle |
0,1073692671 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.SQPowerThrottle_2 |
0,2080325631 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.UVDWatermark |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.VCEWatermark |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.aT |
0,u16max |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.arbRefreshState |
0,2 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.bSP |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.displayWatermark |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.dpm2.MaxPS_StepDec |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.dpm2.MaxPS_StepInc |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.dpm2.PSDeltaLimit |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.dpm2.PSDeltaWin |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.dpm2.PSSamplingTime |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.dpm2.TgtAct |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.gen2PCIE |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.high_temp_vddc.index |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.high_temp_vddc.phase_settings |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.high_temp_vddc.value |
0-u16max |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.hysteresisDown |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.hysteresisUp |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.low_temp_vddc.index |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.low_temp_vddc.phase_settings |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.low_temp_vddc.value |
0-u16max |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.mcFlags |
0-3,8-11,25-27 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.mclk.mclk_value |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.mclk.vDLL_CNTL |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.mclk.vMCLK_PWRMGT_CNTL |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.mclk.vMPLL_AD_FUNC_CNTL |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.mclk.vMPLL_DQ_FUNC_CNTL |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.mclk.vMPLL_FUNC_CNTL |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.mclk.vMPLL_FUNC_CNTL_1 |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.mclk.vMPLL_FUNC_CNTL_2 |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.mclk.vMPLL_SS |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.mclk.vMPLL_SS2 |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.mvdd.index |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.mvdd.phase_settings |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.mvdd.value |
0-u16max |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.padding |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.sclk.sclk_value |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.sclk.vCG_SPLL_FUNC_CNTL |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.sclk.vCG_SPLL_FUNC_CNTL_2 |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.sclk.vCG_SPLL_FUNC_CNTL_3 |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.sclk.vCG_SPLL_FUNC_CNTL_4 |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM_2 |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.stateFlags |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.std_vddc.phase_settings |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.std_vddc.value |
0-u16max |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.strobeMode |
0-31 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.vddc.phase_settings |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.vddc.value |
0-u16max |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.vddci.phase_settings |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.level.vddci.value |
0-u16max |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.levelCount |
0-1 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.padding2 |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.ULVState.padding3 |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.dpm2Params.NearTDPLimit |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.dpm2Params.SafePowerLimit |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.dpm2Params.TDPLimit |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.driverState.flags |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.driverState.levelCount |
0-1 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.extraFlags |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.flags |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.SQPowerThrottle |
0,1073692671 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.SQPowerThrottle_2 |
0,2080325631 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.aT |
0,u16max |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.bSP |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.gen2PCIE |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.mcFlags |
0,3 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.mclk.mclk_value |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.mclk.vDLL_CNTL |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.mclk.vMCLK_PWRMGT_CNTL |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.mclk.vMPLL_AD_FUNC_CNTL |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.mclk.vMPLL_DQ_FUNC_CNTL |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.mclk.vMPLL_FUNC_CNTL |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.mclk.vMPLL_FUNC_CNTL_1 |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.mclk.vMPLL_FUNC_CNTL_2 |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.mclk.vMPLL_SS |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.mclk.vMPLL_SS2 |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.mvdd.index |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.mvdd.value |
0-u16max |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.sclk.sclk_value |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.sclk.vCG_SPLL_FUNC_CNTL |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.sclk.vCG_SPLL_FUNC_CNTL_2 |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.sclk.vCG_SPLL_FUNC_CNTL_3 |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.sclk.vCG_SPLL_FUNC_CNTL_4 |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.std_vddc.value |
0-u16max |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.strobeMode |
0-31 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.vddc.phase_settings |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.vddc.value |
0-u16max |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.level.vddci.value |
0-u16max |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.initialState.levelCount |
0-1 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.maxVDDCIndexInPPTable |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.systemFlags |
0-255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->smc_statetable.thermalProtectType |
0-1,255 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->soft_regs_start |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->spll_table_start |
1-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.dpm.priv->state_table_start |
0-4294967295 |
| PARAM_VALUE |
0 |
rdev->pm.mutex.first_waiter |
0,4096-ptr_max |
| PARAM_VALUE |
0 |
rdev->pm.mutex.osq.tail.counter |
0-s32max |
| PARAM_VALUE |
0 |
rdev->pm.mutex.wait_lock.owner |
(-1) |
| PARAM_VALUE |
0 |
rdev->pm.mutex.wait_lock.owner_cpu |
u32max |
| PARAM_VALUE |
0 |
rdev->pm.pm_method |
2 |
| PARAM_VALUE |
0 |
rdev->smc_fw |
4096-ptr_max |
| PARAM_VALUE |
0 |
rdev->smc_idx_lock.rlock.dep_map->name |
0-255 |
| PARAM_VALUE |
0 |
rdev->uvd.vcpu_bo->tbo.bdev->pool.dev->iommu->attach_deferred |
0-1 |
| PARAM_VALUE |
0 |
rdev->wb.wb_obj->tbo.bdev->pool.dev->iommu->attach_deferred |
0-1 |
| PARAM_VALUE |
0 |
*rdev->pm.dpm.priv->smc_statetable->lowSMIO |
0-4294967295 |
| BUF_SIZE |
0 |
rdev |
s32min-(-1),1-s32max |
| BUF_SIZE |
0 |
rdev |
s32min-(-1),1-s32max |
| BUF_SIZE |
0 |
rdev->agp |
(-1),144 |
| CAPPED_DATA |
0 |
rdev->pm.dpm.priv->acpi_vddc |
1 |
| CAPPED_DATA |
0 |
rdev->pm.dpm.priv->vddc_voltage_table.count |
1 |
| CAPPED_DATA |
0 |
rdev->rmmio_size |
1 |
| DATA_SOURCE |
0 |
rdev |
$0 |
| RX_PATH |
|
|
|
| TASK_NOT_RUNNING |
|
|
|
| NOCHECK_CALL |
|
|
|
| HOST_DATA |
0 |
rdev->gart.num_cpu_pages |
0-524287[c] |
| HOST_DATA |
0 |
rdev->mc.aper_base |
0-1099511627775[c] |
| HOST_DATA |
0 |
rdev->mc.gtt_size |
0-s32max[c] |
| HOST_DATA |
0 |
rdev->mc.gtt_start |
0-u64max[c] |
| HOST_DATA |
0 |
rdev->mc.mc_vram_size |
0-4503599626321920 |
| HOST_DATA |
0 |
rdev->mc.real_vram_size |
0-4503599626321920 |
| HOST_DATA |
0 |
rdev->mc.vram_end |
0-4504699121172479,u64max[c] |
| HOST_DATA |
0 |
rdev->mc.vram_start |
0-9223372036854775807[c] |
| NO_OVERFLOW_SIMPLE |
0 |
rdev->pm.current_power_state_index |
|
| NO_OVERFLOW_SIMPLE |
0 |
rdev->pm.default_power_state_index |
|
| NO_OVERFLOW_SIMPLE |
0 |
rdev->pm.num_power_states |
|
| NO_OVERFLOW_SIMPLE |
0 |
rdev->rmmio_size |
|
| LOCK2 |
|
&rdev->pm.mutex |
|
| TYPE_LOCK |
|
(struct radeon_pm)->mutex |
|