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Defined in 1 files as a prototype:

Defined in 1 files as a function:

Referenced in 3 files:

Smatch caller information:

drivers/gpu/drm/xe/xe_gt_idle.c xe_gt_idle_enable_pg() -> xe_hw_engine_mask_per_class()

Type Parameter Key Value
PARAM_VALUE 0 gt 4096-ptr_max
PARAM_VALUE 1 engine_class 1
DATA_SOURCE 0 gt $0
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 gt->uc.guc->ct.msg 0-255
HOST_DATA 0 gt->uc.guc.ct->msg 0-255

drivers/gpu/drm/xe/xe_gt_idle.c xe_gt_idle_enable_pg() -> xe_hw_engine_mask_per_class()

Type Parameter Key Value
PARAM_VALUE 0 gt 4096-ptr_max
PARAM_VALUE 1 engine_class 2
DATA_SOURCE 0 gt $0
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 gt->uc.guc->ct.msg 0-255
HOST_DATA 0 gt->uc.guc.ct->msg 0-255

drivers/gpu/drm/xe/xe_gt_idle.c xe_gt_idle_pg_print() -> xe_hw_engine_mask_per_class()

Type Parameter Key Value
PARAM_VALUE 0 gt 4096-ptr_max
PARAM_VALUE 1 engine_class 1
BUF_SIZE 0 gt s32min-(-2),1-s32max
BUF_SIZE 0 gt s32min-(-2),1-s32max
DATA_SOURCE 0 gt $0
RX_PATH
TASK_NOT_RUNNING
UNITS 0 gt unit_array_size
LOCK2 &m->lock
TYPE_LOCK (struct seq_file)->lock

drivers/gpu/drm/xe/xe_gt_idle.c xe_gt_idle_pg_print() -> xe_hw_engine_mask_per_class()

Type Parameter Key Value
PARAM_VALUE 0 gt 4096-ptr_max
PARAM_VALUE 1 engine_class 2
BUF_SIZE 0 gt s32min-(-2),1-s32max
BUF_SIZE 0 gt s32min-(-2),1-s32max
DATA_SOURCE 0 gt $0
RX_PATH
TASK_NOT_RUNNING
UNITS 0 gt unit_array_size
LOCK2 &m->lock
TYPE_LOCK (struct seq_file)->lock

drivers/gpu/drm/xe/xe_irq.c gt_irq_reset() -> xe_hw_engine_mask_per_class()

Type Parameter Key Value
PARAM_VALUE 0 gt 1-u64max
PARAM_VALUE 1 engine_class 5
RX_PATH
TASK_NOT_RUNNING

drivers/gpu/drm/xe/xe_irq.c gt_irq_reset() -> xe_hw_engine_mask_per_class()

Type Parameter Key Value
PARAM_VALUE 0 gt 1-u64max
PARAM_VALUE 1 engine_class 3
RX_PATH
TASK_NOT_RUNNING

drivers/gpu/drm/xe/xe_irq.c gt_irq_reset() -> xe_hw_engine_mask_per_class()

Type Parameter Key Value
PARAM_VALUE 0 gt 1-u64max
PARAM_VALUE 1 engine_class 4
RX_PATH
TASK_NOT_RUNNING

drivers/gpu/drm/xe/xe_irq.c xe_irq_enable_hwe() -> xe_hw_engine_mask_per_class()

Type Parameter Key Value
PARAM_VALUE 0 gt 4096-ptr_max
PARAM_VALUE 1 engine_class 5
DATA_SOURCE 0 gt $0
RX_PATH
TASK_NOT_RUNNING
NO_OVERFLOW_SIMPLE 0 gt->uc.guc.relay.pool.min_nr
HALF_LOCKED2 &pool->lock

drivers/gpu/drm/xe/xe_irq.c xe_irq_enable_hwe() -> xe_hw_engine_mask_per_class()

Type Parameter Key Value
PARAM_VALUE 0 gt 4096-ptr_max
PARAM_VALUE 1 engine_class 3
DATA_SOURCE 0 gt $0
RX_PATH
TASK_NOT_RUNNING
NO_OVERFLOW_SIMPLE 0 gt->uc.guc.relay.pool.min_nr
HALF_LOCKED2 &pool->lock

drivers/gpu/drm/xe/xe_irq.c xe_irq_enable_hwe() -> xe_hw_engine_mask_per_class()

Type Parameter Key Value
PARAM_VALUE 0 gt 4096-ptr_max
PARAM_VALUE 1 engine_class 1
DATA_SOURCE 0 gt $0
RX_PATH
TASK_NOT_RUNNING
NO_OVERFLOW_SIMPLE 0 gt->uc.guc.relay.pool.min_nr
HALF_LOCKED2 &pool->lock

drivers/gpu/drm/xe/xe_irq.c xe_irq_enable_hwe() -> xe_hw_engine_mask_per_class()

Type Parameter Key Value
PARAM_VALUE 0 gt 4096-ptr_max
PARAM_VALUE 1 engine_class 2
DATA_SOURCE 0 gt $0
RX_PATH
TASK_NOT_RUNNING
NO_OVERFLOW_SIMPLE 0 gt->uc.guc.relay.pool.min_nr
HALF_LOCKED2 &pool->lock

drivers/gpu/drm/xe/xe_irq.c xe_irq_enable_hwe() -> xe_hw_engine_mask_per_class()

Type Parameter Key Value
PARAM_VALUE 0 gt 4096-ptr_max
PARAM_VALUE 1 engine_class 4
DATA_SOURCE 0 gt $0
RX_PATH
TASK_NOT_RUNNING
NO_OVERFLOW_SIMPLE 0 gt->uc.guc.relay.pool.min_nr
HALF_LOCKED2 &pool->lock

drivers/gpu/drm/xe/xe_guc.c guc_ctl_wa_flags() -> xe_hw_engine_mask_per_class()

Type Parameter Key Value
PARAM_VALUE 0 gt 4096-ptr_max
PARAM_VALUE 1 engine_class 0
DATA_SOURCE 0 gt r guc_to_gt
RX_PATH
TASK_NOT_RUNNING