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Defined in 1 files as a prototype:

Defined in 1 files as a function:

Referenced in 3 files:

Smatch caller information:

drivers/gpu/drm/amd/amdgpu/soc21.c soc21_common_early_init() -> xgpu_nv_mailbox_set_irq_funcs()

Type Parameter Key Value
PARAM_VALUE 0 adev 4096-ptr_max
BUF_SIZE 0 adev->asic_funcs 192
BUF_SIZE 0 adev->reg.didt.rreg 8
BUF_SIZE 0 adev->reg.didt.wreg 8
BUF_SIZE 0 adev->reg.pcie.port_rreg 8
BUF_SIZE 0 adev->reg.pcie.port_wreg 8
BUF_SIZE 0 adev->reg.pcie.rreg 8
BUF_SIZE 0 adev->reg.pcie.rreg64 8
BUF_SIZE 0 adev->reg.pcie.wreg 8
BUF_SIZE 0 adev->reg.pcie.wreg64 8
BIT_INFO 0 adev->virt.caps 0x4,0xffffffffffffffff
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HOST_DATA 0 adev->external_rev_id 1-47,64-95,128-143,193-223[c]
HOST_DATA 0 adev->rev_id 0-15[c]
HALF_LOCKED2 &pool->lock

drivers/gpu/drm/amd/amdgpu/nv.c nv_common_early_init() -> xgpu_nv_mailbox_set_irq_funcs()

Type Parameter Key Value
PARAM_VALUE 0 adev 4096-ptr_max
BUF_SIZE 0 adev->asic_funcs 192
BUF_SIZE 0 adev->reg.didt.rreg 8
BUF_SIZE 0 adev->reg.didt.wreg 8
BUF_SIZE 0 adev->reg.pcie.port_rreg 8
BUF_SIZE 0 adev->reg.pcie.port_wreg 8
BUF_SIZE 0 adev->reg.pcie.rreg 8
BUF_SIZE 0 adev->reg.pcie.rreg64 8
BUF_SIZE 0 adev->reg.pcie.wreg 8
BUF_SIZE 0 adev->reg.pcie.wreg64 8
BIT_INFO 0 adev->virt.caps 0x4,0xffffffffffffffff
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HOST_DATA 0 adev->external_rev_id 1-35,40-85,130-145[c]
HOST_DATA 0 adev->rev_id 0-15[c]
HALF_LOCKED2 &pool->lock

drivers/gpu/drm/amd/amdgpu/soc24.c soc24_common_early_init() -> xgpu_nv_mailbox_set_irq_funcs()

Type Parameter Key Value
PARAM_VALUE 0 adev 4096-ptr_max
BUF_SIZE 0 adev->asic_funcs 192
BUF_SIZE 0 adev->reg.pcie.port_rreg 8
BUF_SIZE 0 adev->reg.pcie.port_wreg 8
BUF_SIZE 0 adev->reg.pcie.rreg 8
BUF_SIZE 0 adev->reg.pcie.rreg64 8
BUF_SIZE 0 adev->reg.pcie.wreg 8
BUF_SIZE 0 adev->reg.pcie.wreg64 8
BIT_INFO 0 adev->virt.caps 0x4,0xffffffffffffffff
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HOST_DATA 0 adev->external_rev_id 64-95[c]
HOST_DATA 0 adev->rev_id 0-15[c]
HALF_LOCKED2 &pool->lock