# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/rockchip-inno-csi-dphy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip SoC MIPI RX0 D-PHY

maintainers:
  - Heiko Stuebner <heiko@sntech.de>

description: |
  The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP which
  connects to the ISP1 (Image Signal Processing unit v1.0) for CSI cameras.

properties:
  compatible:
    enum:
      - rockchip,px30-csi-dphy
      - rockchip,rk1808-csi-dphy
      - rockchip,rk3326-csi-dphy
      - rockchip,rk3368-csi-dphy
      - rockchip,rk3568-csi-dphy
      - rockchip,rk3588-csi-dphy

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: pclk

  '#phy-cells':
    const: 0

  power-domains:
    description: Video in/out power domain.
    maxItems: 1

  resets:
    items:
      - description: APB reset line
      - description: PHY reset line
    minItems: 1

  reset-names:
    items:
      - const: apb
      - const: phy
    minItems: 1

  rockchip,grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Some additional phy settings are access through GRF regs.

  rockchip,clk-lane-phase:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 7
    default: 3
    description:
      Clock lane sampling phase selection (hardware tap index 0–7). Each step
      corresponds to an approximately 40 ps delay as described in the hardware
      specification.

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#phy-cells'
  - resets
  - reset-names
  - rockchip,grf

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - rockchip,px30-csi-dphy
              - rockchip,rk1808-csi-dphy
              - rockchip,rk3326-csi-dphy
              - rockchip,rk3368-csi-dphy
    then:
      required:
        - power-domains
  - if:
      properties:
        compatible:
          contains:
            enum:
              - rockchip,px30-csi-dphy
              - rockchip,rk1808-csi-dphy
              - rockchip,rk3326-csi-dphy
              - rockchip,rk3368-csi-dphy
              - rockchip,rk3568-csi-dphy
    then:
      properties:
        resets:
          maxItems: 1

        reset-names:
          maxItems: 1
    else:
      properties:
        resets:
          minItems: 2

        reset-names:
          minItems: 2

additionalProperties: false

examples:
  - |

    csi_dphy: phy@ff2f0000 {
        compatible = "rockchip,px30-csi-dphy";
        reg = <0xff2f0000 0x4000>;
        clocks = <&cru 1>;
        clock-names = "pclk";
        #phy-cells = <0>;
        power-domains = <&power 1>;
        resets = <&cru 1>;
        reset-names = "apb";
        rockchip,grf = <&grf>;
    };
  - |
    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
    #include <dt-bindings/reset/rockchip,rk3588-cru.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        phy@fedc0000 {
            compatible = "rockchip,rk3588-csi-dphy";
            reg = <0x0 0xfedc0000 0x0 0x8000>;
            clocks = <&cru PCLK_CSIPHY0>;
            clock-names = "pclk";
            #phy-cells = <0>;
            resets = <&cru SRST_P_CSIPHY0>, <&cru SRST_CSIPHY0>;
            reset-names = "apb", "phy";
            rockchip,grf = <&csidphy0_grf>;
        };
    };