Defined in 2 files as a function:
- drivers/gpu/drm/amd/display/dc/bios/bios_parser.c, line 863 (as a function)
- drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c, line 1721 (as a function)
Referenced in 2 files:
- drivers/gpu/drm/amd/display/dc/bios/bios_parser.c, line 2975
- drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c, line 3781
Smatch caller information:
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_clock_source.c dce110_clock_source_power_down() -> (struct dc_vbios_funcs)->set_pixel_clock()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dcb | 4096-ptr_max |
| PARAM_VALUE | 0 | dcb->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | bp_params | 4507914846954598400 |
| PARAM_VALUE | 1 | bp_params->color_depth | 0 |
| PARAM_VALUE | 1 | bp_params->controller_id | 0 |
| PARAM_VALUE | 1 | bp_params->dfs_bypass_display_clock | 0 |
| PARAM_VALUE | 1 | bp_params->encoder_object_id.enum_id | 0 |
| PARAM_VALUE | 1 | bp_params->encoder_object_id.id | 0 |
| PARAM_VALUE | 1 | bp_params->encoder_object_id.reserved | 0 |
| PARAM_VALUE | 1 | bp_params->encoder_object_id.type | 0 |
| PARAM_VALUE | 1 | bp_params->feedback_divider | 0 |
| PARAM_VALUE | 1 | bp_params->flags.FORCE_PROGRAMMING_OF_PLL | 1 |
| PARAM_VALUE | 1 | bp_params->flags.PROGRAM_PHY_PLL_ONLY | 0 |
| PARAM_VALUE | 1 | bp_params->flags.SET_DISPCLK_DFS_BYPASS | 0 |
| PARAM_VALUE | 1 | bp_params->flags.SET_EXTERNAL_REF_DIV_SRC | 0 |
| PARAM_VALUE | 1 | bp_params->flags.SET_GENLOCK_REF_DIV_SRC | 0 |
| PARAM_VALUE | 1 | bp_params->flags.SET_XTALIN_REF_SRC | 0 |
| PARAM_VALUE | 1 | bp_params->flags.SUPPORT_YUV_420 | 0 |
| PARAM_VALUE | 1 | bp_params->flags.USE_E_CLOCK_AS_SOURCE_FOR_D_CLOCK | 0 |
| PARAM_VALUE | 1 | bp_params->fractional_feedback_divider | 0 |
| PARAM_VALUE | 1 | bp_params->pixel_clock_post_divider | 0 |
| PARAM_VALUE | 1 | bp_params->reference_divider | 0 |
| PARAM_VALUE | 1 | bp_params->signal_type | 0 |
| PARAM_VALUE | 1 | bp_params->target_pixel_clock_100hz | 0 |
| CONTAINER | 0 | *(-168-0+0) | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING |
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_clock_source.c dce110_program_pix_clk() -> (struct dc_vbios_funcs)->set_pixel_clock()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dcb | 4096-ptr_max |
| PARAM_VALUE | 0 | dcb->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dcb->funcs->enable_spread_spectrum_on_ppll | 0,4096-ptr_max |
| PARAM_VALUE | 1 | bp_params | 7615548341973893120 |
| PARAM_VALUE | 1 | bp_params->color_depth | 0-3 |
| PARAM_VALUE | 1 | bp_params->dfs_bypass_display_clock | 0 |
| PARAM_VALUE | 1 | bp_params->flags.FORCE_PROGRAMMING_OF_PLL | 0 |
| PARAM_VALUE | 1 | bp_params->flags.PROGRAM_PHY_PLL_ONLY | 0 |
| PARAM_VALUE | 1 | bp_params->flags.SET_DISPCLK_DFS_BYPASS | 0 |
| PARAM_VALUE | 1 | bp_params->flags.SET_GENLOCK_REF_DIV_SRC | 0 |
| PARAM_VALUE | 1 | bp_params->flags.SET_XTALIN_REF_SRC | 0 |
| PARAM_VALUE | 1 | bp_params->flags.SUPPORT_YUV_420 | 0 |
| PARAM_VALUE | 1 | bp_params->flags.USE_E_CLOCK_AS_SOURCE_FOR_D_CLOCK | 0 |
| CONTAINER | 0 | *(-168-0+0) | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING |
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_clock_source.c dce112_program_pix_clk() -> (struct dc_vbios_funcs)->set_pixel_clock()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dcb | 4096-ptr_max |
| PARAM_VALUE | 0 | dcb->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dcb->funcs->enable_spread_spectrum_on_ppll | 0,4096-ptr_max |
| PARAM_VALUE | 1 | bp_params | 8347447438034644992 |
| PARAM_VALUE | 1 | bp_params->color_depth | 0 |
| PARAM_VALUE | 1 | bp_params->dfs_bypass_display_clock | 0 |
| PARAM_VALUE | 1 | bp_params->feedback_divider | 0 |
| PARAM_VALUE | 1 | bp_params->flags.FORCE_PROGRAMMING_OF_PLL | 0 |
| PARAM_VALUE | 1 | bp_params->flags.PROGRAM_PHY_PLL_ONLY | 0 |
| PARAM_VALUE | 1 | bp_params->flags.SET_DISPCLK_DFS_BYPASS | 0 |
| PARAM_VALUE | 1 | bp_params->flags.SET_EXTERNAL_REF_DIV_SRC | 0 |
| PARAM_VALUE | 1 | bp_params->flags.USE_E_CLOCK_AS_SOURCE_FOR_D_CLOCK | 0 |
| PARAM_VALUE | 1 | bp_params->fractional_feedback_divider | 0 |
| PARAM_VALUE | 1 | bp_params->pixel_clock_post_divider | 0 |
| PARAM_VALUE | 1 | bp_params->reference_divider | 0 |
| CONTAINER | 0 | *(-168-0+0) | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING |
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_clock_source.c dcn31_program_pix_clk() -> (struct dc_vbios_funcs)->set_pixel_clock()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dcb | 4096-ptr_max |
| PARAM_VALUE | 0 | dcb->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | bp_params | 6810663314356273152 |
| PARAM_VALUE | 1 | bp_params->color_depth | 0-3 |
| PARAM_VALUE | 1 | bp_params->dfs_bypass_display_clock | 0 |
| PARAM_VALUE | 1 | bp_params->feedback_divider | 0 |
| PARAM_VALUE | 1 | bp_params->flags.FORCE_PROGRAMMING_OF_PLL | 0 |
| PARAM_VALUE | 1 | bp_params->flags.PROGRAM_PHY_PLL_ONLY | 0 |
| PARAM_VALUE | 1 | bp_params->flags.SET_DISPCLK_DFS_BYPASS | 0 |
| PARAM_VALUE | 1 | bp_params->flags.SET_EXTERNAL_REF_DIV_SRC | 0 |
| PARAM_VALUE | 1 | bp_params->flags.USE_E_CLOCK_AS_SOURCE_FOR_D_CLOCK | 0 |
| PARAM_VALUE | 1 | bp_params->fractional_feedback_divider | 0 |
| PARAM_VALUE | 1 | bp_params->pixel_clock_post_divider | 0 |
| PARAM_VALUE | 1 | bp_params->reference_divider | 0 |
| PARAM_VALUE | 1 | bp_params->signal_type | 0-31,33-63,65-127,129-255,257-511,513-u32max |
| CONTAINER | 0 | *(-168-0+0) | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING |
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_clock_source.c dcn401_program_pix_clk() -> (struct dc_vbios_funcs)->set_pixel_clock()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dcb | 4096-ptr_max |
| PARAM_VALUE | 0 | dcb->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | bp_params | 6367164413990416384 |
| PARAM_VALUE | 1 | bp_params->color_depth | 0-3 |
| PARAM_VALUE | 1 | bp_params->dfs_bypass_display_clock | 0 |
| PARAM_VALUE | 1 | bp_params->feedback_divider | 0 |
| PARAM_VALUE | 1 | bp_params->flags.FORCE_PROGRAMMING_OF_PLL | 0 |
| PARAM_VALUE | 1 | bp_params->flags.PROGRAM_PHY_PLL_ONLY | 0 |
| PARAM_VALUE | 1 | bp_params->flags.SET_DISPCLK_DFS_BYPASS | 0 |
| PARAM_VALUE | 1 | bp_params->flags.SET_EXTERNAL_REF_DIV_SRC | 0 |
| PARAM_VALUE | 1 | bp_params->flags.USE_E_CLOCK_AS_SOURCE_FOR_D_CLOCK | 0 |
| PARAM_VALUE | 1 | bp_params->fractional_feedback_divider | 0 |
| PARAM_VALUE | 1 | bp_params->pixel_clock_post_divider | 0 |
| PARAM_VALUE | 1 | bp_params->reference_divider | 0 |
| PARAM_VALUE | 1 | bp_params->signal_type | 1-2,4 |
| PARAM_VALUE | 1 | bp_params->target_pixel_clock_100hz | 0-6000000 |
| CONTAINER | 0 | *(-168-0+0) | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING |