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Defined in 1 files as a prototype:

Defined in 1 files as a function:

Referenced in 2 files:

Smatch caller information:

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c apply_ctx_interdependent_lock() -> (struct hw_sequencer_funcs)->pipe_control_lock()

Type Parameter Key Value
PARAM_VALUE 0 dc 4096-ptr_max
PARAM_VALUE 0 dc->current_state->res_ctx.pipe_ctx 4096-ptr_max
PARAM_VALUE 0 dc->hwss.interdependent_update_lock 0
PARAM_VALUE 0 dc->res_pool 4096-ptr_max
PARAM_VALUE 0 dc->res_pool->pipe_count 1-u32max
PARAM_VALUE 1 pipe 4096-ptr_max
PARAM_VALUE 1 pipe->stream 1-u64max
PARAM_VALUE 1 pipe->top_pipe 0
CAPPED_DATA 1 pipe->stream 1
DATA_SOURCE 0 dc $0
DATA_SOURCE 2 lock $3
CONTAINER 0 -192-218664+0 $(-1)
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn10/dcn10_hwseq.c dcn10_lock_all_pipes() -> (struct hw_sequencer_funcs)->pipe_control_lock()

Type Parameter Key Value
PARAM_VALUE 0 dc 4096-ptr_max
PARAM_VALUE 0 dc->current_state->res_ctx.pipe_ctx 4096-ptr_max
PARAM_VALUE 0 dc->hwss.interdependent_update_lock 1-u64max
PARAM_VALUE 0 dc->res_pool 4096-ptr_max
PARAM_VALUE 0 dc->res_pool->pipe_count 1-u32max
PARAM_VALUE 1 pipe 4096-ptr_max
PARAM_VALUE 1 pipe->stream 1-u64max
PARAM_VALUE 1 pipe->stream_res.tg 4096-ptr_max
PARAM_VALUE 1 pipe->stream_res.tg->funcs 4096-ptr_max
PARAM_VALUE 1 pipe->top_pipe 0
PARAM_VALUE 2 lock 1
DATA_SOURCE 0 dc $0
CONTAINER 0 -192-218664+0 $(-1)
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn10/dcn10_hwseq.c dcn10_lock_all_pipes() -> (struct hw_sequencer_funcs)->pipe_control_lock()

Type Parameter Key Value
PARAM_VALUE 0 dc 4096-ptr_max
PARAM_VALUE 0 dc->current_state->res_ctx.pipe_ctx 4096-ptr_max
PARAM_VALUE 0 dc->hwss.interdependent_update_lock 1-u64max
PARAM_VALUE 0 dc->res_pool 4096-ptr_max
PARAM_VALUE 0 dc->res_pool->pipe_count 1-u32max
PARAM_VALUE 1 pipe 4096-ptr_max
PARAM_VALUE 1 pipe->stream 1-u64max
PARAM_VALUE 1 pipe->stream_res.tg 4096-ptr_max
PARAM_VALUE 1 pipe->stream_res.tg->funcs 4096-ptr_max
PARAM_VALUE 1 pipe->top_pipe 0
PARAM_VALUE 2 lock 0
DATA_SOURCE 0 dc $0
CONTAINER 0 -192-218664+0 $(-1)
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn401/dcn401_hwseq.c dcn401_interdependent_update_lock() -> (struct hw_sequencer_funcs)->pipe_control_lock()

Type Parameter Key Value
PARAM_VALUE 0 dc 4096-ptr_max
PARAM_VALUE 0 dc->hwss.interdependent_update_lock 1-u64max
PARAM_VALUE 0 dc->res_pool 4096-ptr_max
PARAM_VALUE 0 dc->res_pool->pipe_count 1-u32max
PARAM_VALUE 1 pipe 4096-ptr_max
PARAM_VALUE 1 pipe->prev_odm_pipe 0
PARAM_VALUE 1 pipe->stream 1-u64max
PARAM_VALUE 1 pipe->stream_res.tg 4096-ptr_max
PARAM_VALUE 1 pipe->stream_res.tg->funcs 4096-ptr_max
PARAM_VALUE 1 pipe->top_pipe 0
PARAM_VALUE 2 lock 1
DATA_SOURCE 0 dc $0
CONTAINER 0 -192-218664+0 $(-1)
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn401/dcn401_hwseq.c dcn401_interdependent_update_lock() -> (struct hw_sequencer_funcs)->pipe_control_lock()

Type Parameter Key Value
PARAM_VALUE 0 dc 4096-ptr_max
PARAM_VALUE 0 dc->current_state->res_ctx.pipe_ctx 4096-ptr_max
PARAM_VALUE 0 dc->hwss.interdependent_update_lock 1-u64max
PARAM_VALUE 0 dc->res_pool 4096-ptr_max
PARAM_VALUE 0 dc->res_pool->pipe_count 1-u32max
PARAM_VALUE 0 dc->scratch.pipes_to_unlock_first 4096-ptr_max
PARAM_VALUE 1 pipe 4096-ptr_max
PARAM_VALUE 1 pipe->prev_odm_pipe 0
PARAM_VALUE 1 pipe->stream 1-u64max
PARAM_VALUE 1 pipe->stream_res.tg 4096-ptr_max
PARAM_VALUE 1 pipe->stream_res.tg->funcs 4096-ptr_max
PARAM_VALUE 1 pipe->top_pipe 0
PARAM_VALUE 2 lock 0
DATA_SOURCE 0 dc $0
CONTAINER 0 -192-218664+0 $(-1)
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn401/dcn401_hwseq.c dcn401_interdependent_update_lock() -> (struct hw_sequencer_funcs)->pipe_control_lock()

Type Parameter Key Value
PARAM_VALUE 0 dc 4096-ptr_max
PARAM_VALUE 0 dc->hwss.interdependent_update_lock 1-u64max
PARAM_VALUE 0 dc->res_pool 4096-ptr_max
PARAM_VALUE 0 dc->res_pool->pipe_count 1-u32max
PARAM_VALUE 0 dc->scratch.pipes_to_unlock_first 4096-ptr_max
PARAM_VALUE 1 pipe 4096-ptr_max
PARAM_VALUE 1 pipe->prev_odm_pipe 0
PARAM_VALUE 1 pipe->stream 1-u64max
PARAM_VALUE 1 pipe->stream_res.tg 4096-ptr_max
PARAM_VALUE 1 pipe->stream_res.tg->funcs 4096-ptr_max
PARAM_VALUE 1 pipe->top_pipe 0
PARAM_VALUE 2 lock 0
CAPPED_DATA 0 dc->res_pool->pipe_count 1
DATA_SOURCE 0 dc $0
CONTAINER 0 -192-218664+0 $(-1)
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn32/dcn32_hwseq.c dcn32_interdependent_update_lock() -> (struct hw_sequencer_funcs)->pipe_control_lock()

Type Parameter Key Value
PARAM_VALUE 0 dc 4096-ptr_max
PARAM_VALUE 0 dc->hwss.interdependent_update_lock 1-u64max
PARAM_VALUE 0 dc->res_pool 4096-ptr_max
PARAM_VALUE 0 dc->res_pool->pipe_count 1-u32max
PARAM_VALUE 1 pipe 4096-ptr_max
PARAM_VALUE 1 pipe->prev_odm_pipe 0
PARAM_VALUE 1 pipe->stream 1-u64max
PARAM_VALUE 1 pipe->stream_res.tg 4096-ptr_max
PARAM_VALUE 1 pipe->stream_res.tg->funcs 4096-ptr_max
PARAM_VALUE 1 pipe->top_pipe 0
PARAM_VALUE 2 lock 1
DATA_SOURCE 0 dc $0
CONTAINER 0 -192-218664+0 $(-1)
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn32/dcn32_hwseq.c dcn32_interdependent_update_lock() -> (struct hw_sequencer_funcs)->pipe_control_lock()

Type Parameter Key Value
PARAM_VALUE 0 dc 4096-ptr_max
PARAM_VALUE 0 dc->hwss.interdependent_update_lock 1-u64max
PARAM_VALUE 0 dc->res_pool 4096-ptr_max
PARAM_VALUE 0 dc->res_pool->pipe_count 1-u32max
PARAM_VALUE 1 pipe 4096-ptr_max
PARAM_VALUE 1 pipe->prev_odm_pipe 0
PARAM_VALUE 1 pipe->stream 1-u64max
PARAM_VALUE 1 pipe->stream_res.tg 4096-ptr_max
PARAM_VALUE 1 pipe->stream_res.tg->funcs 4096-ptr_max
PARAM_VALUE 1 pipe->top_pipe 0
PARAM_VALUE 2 lock 0
DATA_SOURCE 0 dc $0
CONTAINER 0 -192-218664+0 $(-1)
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_hw_sequencer.c hwss_cursor_lock() -> (struct hw_sequencer_funcs)->cursor_lock()

Type Parameter Key Value
PARAM_VALUE 0 dc 4096-ptr_max
PARAM_VALUE 0 dc->hwss.cursor_lock 1-u64max
CONTAINER 0 -216-218664+0 $(-1)
NOCHECK_CALL