/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*/
#include "dm_services.h"
#include "amdgpu.h"
#include "dc.h"
#include "core_status.h"
#include "core_types.h"
#include "hw_sequencer.h"
#include "dce/dce_hwseq.h"
#include "hw/dccg.h"
#include "resource.h"
#include "dc_state.h"
#include "dc_state_priv.h"
#include "dc_plane.h"
#include "dc_plane_priv.h"
#include "dc_stream_priv.h"
#include "gpio_service_interface.h"
#include "clk_mgr.h"
#include "clock_source.h"
#include "dc_bios_types.h"
#include "bios_parser_interface.h"
#include "bios/bios_parser_helper.h"
#include "include/irq_service_interface.h"
#include "transform.h"
#include "dmcu.h"
#include "dpp.h"
#include "timing_generator.h"
#include "abm.h"
#include "dio/virtual/virtual_link_encoder.h"
#include "hubp.h"
#include "link_hwss.h"
#include "link_encoder.h"
#include "link_enc_cfg.h"
#include "link_service.h"
#include "link/protocols/link_dp_capability.h"
#include "dm_helpers.h"
#include "mem_input.h"
#include "dc_dmub_srv.h"
#include "dsc.h"
#include "vm_helper.h"
#include "dce/dce_i2c.h"
#include "dmub/dmub_srv.h"
#include "dce/dmub_psr.h"
#include "dce/dmub_hw_lock_mgr.h"
#include "dc_trace.h"
#include "hw_sequencer_private.h"
#if defined(CONFIG_DRM_AMD_DC_FP)
#include "dml2_0/dml2_internal_types.h"
#include "soc_and_ip_translator.h"
#endif
#include "dce/dmub_outbox.h"
#define CTX \
dc->ctx
#define DC_LOGGER \
dc->ctx->logger
static const char DC_BUILD_ID[] = "production-build";
/**
* DOC: Overview
*
* DC is the OS-agnostic component of the amdgpu DC driver.
*
* DC maintains and validates a set of structs representing the state of the
* driver and writes that state to AMD hardware
*
* Main DC HW structs:
*
* struct dc - The central struct. One per driver. Created on driver load,
* destroyed on driver unload.
*
* struct dc_context - One per driver.
* Used as a backpointer by most other structs in dc.
*
* struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP
* plugpoints). Created on driver load, destroyed on driver unload.
*
* struct dc_sink - One per display. Created on boot or hotplug.
* Destroyed on shutdown or hotunplug. A dc_link can have a local sink
* (the display directly attached). It may also have one or more remote
* sinks (in the Multi-Stream Transport case)
*
* struct resource_pool - One per driver. Represents the hw blocks not in the
* main pipeline. Not directly accessible by dm.
*
* Main dc state structs:
*
* These structs can be created and destroyed as needed. There is a full set of
* these structs in dc->current_state representing the currently programmed state.
*
* struct dc_state - The global DC state to track global state information,
* such as bandwidth values.
*
* struct dc_stream_state - Represents the hw configuration for the pipeline from
* a framebuffer to a display. Maps one-to-one with dc_sink.
*
* struct dc_plane_state - Represents a framebuffer. Each stream has at least one,
* and may have more in the Multi-Plane Overlay case.
*
* struct resource_context - Represents the programmable state of everything in
* the resource_pool. Not directly accessible by dm.
*
* struct pipe_ctx - A member of struct resource_context. Represents the
* internal hardware pipeline components. Each dc_plane_state has either
* one or two (in the pipe-split case).
*/
/* Private functions */
static inline void elevate_update_type(
struct dc_update_descriptor *descriptor,
enum dc_update_type new_type,
enum dc_lock_descriptor new_locks
)
{
if (new_type > descriptor->update_type)
descriptor->update_type = new_type;
descriptor->lock_descriptor |= new_locks;
}
static void destroy_links(struct dc *dc)
{
uint32_t i;
for (i = 0; i < dc->link_count; i++) {
if (NULL != dc->links[i])
dc->link_srv->destroy_link(&dc->links[i]);
}
}
static uint32_t get_num_of_internal_disp(struct dc_link **links, uint32_t num_links)
{
uint32_t i;
uint32_t count = 0;
for (i = 0; i < num_links; i++) {
if (links[i]->connector_signal == SIGNAL_TYPE_EDP ||
links[i]->is_internal_display)
count++;
}
return count;
}
static int get_seamless_boot_stream_count(struct dc_state *ctx)
{
uint8_t i;
uint8_t seamless_boot_stream_count = 0;
for (i = 0; i < ctx->stream_count; i++)
if (ctx->streams[i]->apply_seamless_boot_optimization)
seamless_boot_stream_count++;
return seamless_boot_stream_count;
}
static bool create_links(
struct dc *dc,
uint32_t num_virtual_links)
{
uint32_t i;
int connectors_num;
struct dc_bios *bios = dc->ctx->dc_bios;
dc->link_count = 0;
connectors_num = bios->funcs->get_connectors_number(bios);
DC_LOG_DC("BIOS object table - number of connectors: %d", connectors_num);
if (connectors_num > ENUM_ID_COUNT) {
dm_error(
"DC: Number of connectors %d exceeds maximum of %d!\n",
connectors_num,
ENUM_ID_COUNT);
return false;
}
dm_output_to_console(
"DC: %s: connectors_num: physical:%d, virtual:%d\n",
__func__,
connectors_num,
num_virtual_links);
/* When getting the number of connectors, the VBIOS reports the number of valid indices,
* but it doesn't say which indices are valid, and not every index has an actual connector.
* So, if we don't find a connector on an index, that is not an error.
*
* - There is no guarantee that the first N indices will be valid
* - VBIOS may report a higher amount of valid indices than there are actual connectors
* - Some VBIOS have valid configurations for more connectors than there actually are
* on the card. This may be because the manufacturer used the same VBIOS for different
* variants of the same card.
*/
for (i = 0; dc->link_count < connectors_num && i < MAX_LINKS; i++) {
struct graphics_object_id connector_id = bios->funcs->get_connector_id(bios, (uint8_t)i);
struct link_init_data link_init_params = {0};
struct dc_link *link;
if (connector_id.id == CONNECTOR_ID_UNKNOWN)
continue;
DC_LOG_DC("BIOS object table - printing link object info for connector number: %d, link_index: %d", i, dc->link_count);
link_init_params.ctx = dc->ctx;
/* next BIOS object table connector */
link_init_params.connector_index = (uint8_t)i;
link_init_params.link_index = dc->link_count;
link_init_params.dc = dc;
link = dc->link_srv->create_link(&link_init_params);
if (link) {
dc->links[dc->link_count] = link;
link->dc = dc;
++dc->link_count;
}
}
DC_LOG_DC("BIOS object table - end");
/* Create a link for each usb4 dpia port */
dc->lowest_dpia_link_index = MAX_LINKS;
for (i = 0; i < dc->res_pool->usb4_dpia_count; i++) {
struct link_init_data link_init_params = {0};
struct dc_link *link;
link_init_params.ctx = dc->ctx;
link_init_params.connector_index = (uint8_t)i;
link_init_params.link_index = dc->link_count;
link_init_params.dc = dc;
link_init_params.is_dpia_link = true;
link = dc->link_srv->create_link(&link_init_params);
if (link) {
if (dc->lowest_dpia_link_index > dc->link_count)
dc->lowest_dpia_link_index = dc->link_count;
dc->links[dc->link_count] = link;
link->dc = dc;
++dc->link_count;
}
}
for (i = 0; i < num_virtual_links; i++) {
struct dc_link *link = kzalloc_obj(*link);
struct encoder_init_data enc_init = {0};
if (link == NULL) {
BREAK_TO_DEBUGGER();
goto failed_alloc;
}
link->link_index = dc->link_count;
dc->links[dc->link_count] = link;
dc->link_count++;
link->ctx = dc->ctx;
link->dc = dc;
link->connector_signal = SIGNAL_TYPE_VIRTUAL;
link->link_id.type = OBJECT_TYPE_CONNECTOR;
link->link_id.id = CONNECTOR_ID_VIRTUAL;
link->link_id.enum_id = ENUM_ID_1;
link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
link->replay_settings.config.replay_version = DC_REPLAY_VERSION_UNSUPPORTED;
link->link_enc = kzalloc_obj(*link->link_enc);
if (!link->link_enc) {
BREAK_TO_DEBUGGER();
goto failed_alloc;
}
link->link_status.dpcd_caps = &link->dpcd_caps;
enc_init.ctx = dc->ctx;
enc_init.channel = CHANNEL_ID_UNKNOWN;
enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
enc_init.transmitter = TRANSMITTER_UNKNOWN;
enc_init.connector = link->link_id;
enc_init.encoder.type = OBJECT_TYPE_ENCODER;
enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
enc_init.encoder.enum_id = ENUM_ID_1;
virtual_link_encoder_construct(link->link_enc, &enc_init);
}
dc->caps.num_of_internal_disp = get_num_of_internal_disp(dc->links, dc->link_count);
return true;
failed_alloc:
return false;
}
/* Create additional DIG link encoder objects if fewer than the platform
* supports were created during link construction. This can happen if the
* number of physical connectors is less than the number of DIGs.
*/
static bool create_link_encoders(struct dc *dc)
{
bool res = true;
unsigned int num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia;
unsigned int num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc;
unsigned int i;
/* A platform without USB4 DPIA endpoints has a fixed mapping between DIG
* link encoders and physical display endpoints and does not require
* additional link encoder objects.
*/
if (num_usb4_dpia == 0)
return res;
/* Create as many link encoder objects as the platform supports. DPIA
* endpoints can be programmably mapped to any DIG.
*/
if (num_dig_link_enc > dc->res_pool->dig_link_enc_count) {
for (i = 0; i < num_dig_link_enc; i++) {
struct link_encoder *link_enc = dc->res_pool->link_encoders[i];
if (!link_enc && dc->res_pool->funcs->link_enc_create_minimal) {
link_enc = dc->res_pool->funcs->link_enc_create_minimal(dc->ctx,
(enum engine_id)(ENGINE_ID_DIGA + i));
if (link_enc) {
dc->res_pool->link_encoders[i] = link_enc;
dc->res_pool->dig_link_enc_count++;
} else {
res = false;
}
}
}
}
return res;
}
/* Destroy any additional DIG link encoder objects created by
* create_link_encoders().
* NB: Must only be called after destroy_links().
*/
static void destroy_link_encoders(struct dc *dc)
{
unsigned int num_usb4_dpia;
unsigned int num_dig_link_enc;
unsigned int i;
if (!dc->res_pool)
return;
num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia;
num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc;
/* A platform without USB4 DPIA endpoints has a fixed mapping between DIG
* link encoders and physical display endpoints and does not require
* additional link encoder objects.
*/
if (num_usb4_dpia == 0)
return;
for (i = 0; i < num_dig_link_enc; i++) {
struct link_encoder *link_enc = dc->res_pool->link_encoders[i];
if (link_enc) {
link_enc->funcs->destroy(&link_enc);
dc->res_pool->link_encoders[i] = NULL;
dc->res_pool->dig_link_enc_count--;
}
}
}
static struct dc_perf_trace *dc_perf_trace_create(void)
{
return kzalloc_obj(struct dc_perf_trace);
}
static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace)
{
kfree(*perf_trace);
*perf_trace = NULL;
}
static bool set_long_vtotal(struct dc *dc, struct dc_stream_state *stream, struct dc_crtc_timing_adjust *adjust)
{
if (!dc || !stream || !adjust)
return false;
if (!dc->current_state)
return false;
int i;
for (i = 0; i < MAX_PIPES; i++) {
struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
if (pipe->stream == stream && pipe->stream_res.tg) {
if (dc->hwss.set_long_vtotal)
dc->hwss.set_long_vtotal(&pipe, 1, adjust->v_total_min, adjust->v_total_max);
return true;
}
}
return false;
}
/**
* dc_stream_get_last_used_drr_vtotal - Looks up the pipe context of
* dc_stream_state and gets the last VTOTAL used by DRR (Dynamic Refresh Rate)
*
* @dc: [in] dc reference
* @stream: [in] Initial dc stream state
* @refresh_rate: [in] new refresh_rate
*
* Return: %true if the pipe context is found and there is an associated
* timing_generator for the DC;
* %false if the pipe context is not found or there is no
* timing_generator for the DC.
*/
bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,
struct dc_stream_state *stream,
uint32_t *refresh_rate)
{
bool status = false;
int i = 0;
dc_exit_ips_for_hw_access(dc);
for (i = 0; i < MAX_PIPES; i++) {
struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
if (pipe->stream == stream && pipe->stream_res.tg) {
/* Only execute if a function pointer has been defined for
* the DC version in question
*/
if (pipe->stream_res.tg->funcs->get_last_used_drr_vtotal) {
pipe->stream_res.tg->funcs->get_last_used_drr_vtotal(pipe->stream_res.tg, refresh_rate);
status = true;
break;
}
}
}
return status;
}
#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
static inline void
dc_stream_forward_dmub_crc_window(struct dc_dmub_srv *dmub_srv,
struct rect *rect, struct otg_phy_mux *mux_mapping, bool is_stop)
{
union dmub_rb_cmd cmd = {0};
cmd.secure_display.roi_info.phy_id = mux_mapping->phy_output_num;
cmd.secure_display.roi_info.otg_id = mux_mapping->otg_output_num;
if (is_stop) {
cmd.secure_display.header.type = DMUB_CMD__SECURE_DISPLAY;
cmd.secure_display.header.sub_type = DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE;
} else {
cmd.secure_display.header.type = DMUB_CMD__SECURE_DISPLAY;
cmd.secure_display.header.sub_type = DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY;
cmd.secure_display.roi_info.x_start = rect->x;
cmd.secure_display.roi_info.y_start = rect->y;
cmd.secure_display.roi_info.x_end = rect->x + rect->width;
cmd.secure_display.roi_info.y_end = rect->y + rect->height;
}
dc_wake_and_execute_dmub_cmd(dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
}
static inline void
dc_stream_forward_dmcu_crc_window(struct dmcu *dmcu,
struct rect *rect, struct otg_phy_mux *mux_mapping, bool is_stop)
{
if (is_stop)
dmcu->funcs->stop_crc_win_update(dmcu, mux_mapping);
else
dmcu->funcs->forward_crc_window(dmcu, rect, mux_mapping);
}
bool
dc_stream_forward_crc_window(struct dc_stream_state *stream,
struct rect *rect, uint8_t phy_id, bool is_stop)
{
struct dmcu *dmcu;
struct dc_dmub_srv *dmub_srv;
struct otg_phy_mux mux_mapping;
struct pipe_ctx *pipe;
int i;
struct dc *dc = stream->ctx->dc;
for (i = 0; i < MAX_PIPES; i++) {
pipe = &dc->current_state->res_ctx.pipe_ctx[i];
if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
break;
}
/* Stream not found */
if (i == MAX_PIPES)
return false;
mux_mapping.phy_output_num = phy_id;
mux_mapping.otg_output_num = pipe->stream_res.tg->inst;
dmcu = dc->res_pool->dmcu;
dmub_srv = dc->ctx->dmub_srv;
/* forward to dmub */
if (dmub_srv)
dc_stream_forward_dmub_crc_window(dmub_srv, rect, &mux_mapping, is_stop);
/* forward to dmcu */
else if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
dc_stream_forward_dmcu_crc_window(dmcu, rect, &mux_mapping, is_stop);
else
return false;
return true;
}
static void
dc_stream_forward_dmub_multiple_crc_window(struct dc_dmub_srv *dmub_srv,
struct crc_window *window, struct otg_phy_mux *mux_mapping, bool stop)
{
int i;
union dmub_rb_cmd cmd = {0};
cmd.secure_display.mul_roi_ctl.phy_id = mux_mapping->phy_output_num;
cmd.secure_display.mul_roi_ctl.otg_id = mux_mapping->otg_output_num;
cmd.secure_display.header.type = DMUB_CMD__SECURE_DISPLAY;
if (stop) {
cmd.secure_display.header.sub_type = DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE;
} else {
cmd.secure_display.header.sub_type = DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY;
for (i = 0; i < MAX_CRC_WINDOW_NUM; i++) {
cmd.secure_display.mul_roi_ctl.roi_ctl[i].x_start = window[i].rect.x;
cmd.secure_display.mul_roi_ctl.roi_ctl[i].y_start = window[i].rect.y;
cmd.secure_display.mul_roi_ctl.roi_ctl[i].x_end = window[i].rect.x + window[i].rect.width;
cmd.secure_display.mul_roi_ctl.roi_ctl[i].y_end = window[i].rect.y + window[i].rect.height;
cmd.secure_display.mul_roi_ctl.roi_ctl[i].enable = window[i].enable;
}
}
dc_wake_and_execute_dmub_cmd(dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
}
bool
dc_stream_forward_multiple_crc_window(struct dc_stream_state *stream,
struct crc_window *window, uint8_t phy_id, bool stop)
{
struct dc_dmub_srv *dmub_srv;
struct otg_phy_mux mux_mapping;
struct pipe_ctx *pipe;
int i;
struct dc *dc = stream->ctx->dc;
for (i = 0; i < MAX_PIPES; i++) {
pipe = &dc->current_state->res_ctx.pipe_ctx[i];
if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
break;
}
/* Stream not found */
if (i == MAX_PIPES)
return false;
mux_mapping.phy_output_num = phy_id;
mux_mapping.otg_output_num = pipe->stream_res.tg->inst;
dmub_srv = dc->ctx->dmub_srv;
/* forward to dmub only. no dmcu support*/
if (dmub_srv)
dc_stream_forward_dmub_multiple_crc_window(dmub_srv, window, &mux_mapping, stop);
else
return false;
return true;
}
#endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
/**
* dc_stream_configure_crc() - Configure CRC capture for the given stream.
* @dc: DC Object
* @stream: The stream to configure CRC on.
* @crc_window: CRC window (x/y start/end) information
* @enable: Enable CRC if true, disable otherwise.
* @continuous: Capture CRC on every frame if true. Otherwise, only capture
* once.
* @idx: Capture CRC on which CRC engine instance
* @reset: Reset CRC engine before the configuration
* @crc_poly_mode: CRC polynomial mode
*
* By default, the entire frame is used to calculate the CRC.
*
* Return: %false if the stream is not found or CRC capture is not supported;
* %true if the stream has been configured.
*/
bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
struct crc_params *crc_window, bool enable, bool continuous,
uint8_t idx, bool reset, enum crc_poly_mode crc_poly_mode)
{
struct pipe_ctx *pipe;
struct crc_params param;
struct timing_generator *tg;
pipe = resource_get_otg_master_for_stream(
&dc->current_state->res_ctx, stream);
/* Stream not found */
if (pipe == NULL)
return false;
dc_exit_ips_for_hw_access(dc);
/* By default, capture the full frame */
param.windowa_x_start = 0;
param.windowa_y_start = 0;
param.windowa_x_end = (uint16_t)pipe->stream->timing.h_addressable;
param.windowa_y_end = (uint16_t)pipe->stream->timing.v_addressable;
param.windowb_x_start = 0;
param.windowb_y_start = 0;
param.windowb_x_end = (uint16_t)pipe->stream->timing.h_addressable;
param.windowb_y_end = (uint16_t)pipe->stream->timing.v_addressable;
param.crc_poly_mode = crc_poly_mode;
if (crc_window) {
param.windowa_x_start = crc_window->windowa_x_start;
param.windowa_y_start = crc_window->windowa_y_start;
param.windowa_x_end = crc_window->windowa_x_end;
param.windowa_y_end = crc_window->windowa_y_end;
param.windowb_x_start = crc_window->windowb_x_start;
param.windowb_y_start = crc_window->windowb_y_start;
param.windowb_x_end = crc_window->windowb_x_end;
param.windowb_y_end = crc_window->windowb_y_end;
}
param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0;
param.odm_mode = pipe->next_odm_pipe ? 1:0;
/* Default to the union of both windows */
param.selection = UNION_WINDOW_A_B;
param.continuous_mode = continuous;
param.enable = enable;
param.crc_eng_inst = idx;
param.reset = reset;
tg = pipe->stream_res.tg;
/* Only call if supported */
if (tg->funcs->configure_crc)
return tg->funcs->configure_crc(tg, ¶m);
DC_LOG_WARNING("CRC capture not supported.");
return false;
}
/**
* dc_stream_get_crc() - Get CRC values for the given stream.
*
* @dc: DC object.
* @stream: The DC stream state of the stream to get CRCs from.
* @idx: index of crc engine to get CRC from
* @r_cr: CRC value for the red component.
* @g_y: CRC value for the green component.
* @b_cb: CRC value for the blue component.
*
* dc_stream_configure_crc needs to be called beforehand to enable CRCs.
*
* Return:
* %false if stream is not found, or if CRCs are not enabled.
*/
bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream, uint8_t idx,
uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
{
int i;
struct pipe_ctx *pipe = NULL;
struct timing_generator *tg;
dc_exit_ips_for_hw_access(dc);
for (i = 0; i < MAX_PIPES; i++) {
pipe = &dc->current_state->res_ctx.pipe_ctx[i];
if (pipe->stream == stream)
break;
}
/* Stream not found */
if (i == MAX_PIPES)
return false;
tg = pipe->stream_res.tg;
if (tg->funcs->get_crc)
return tg->funcs->get_crc(tg, idx, r_cr, g_y, b_cb);
DC_LOG_WARNING("CRC capture not supported.");
return false;
}
void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
enum dc_dynamic_expansion option)
{
/* OPP FMT dyn expansion updates*/
int i;
struct pipe_ctx *pipe_ctx;
dc_exit_ips_for_hw_access(dc);
for (i = 0; i < MAX_PIPES; i++) {
if (dc->current_state->res_ctx.pipe_ctx[i].stream
== stream) {
pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
pipe_ctx->stream_res.opp->dyn_expansion = option;
pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
pipe_ctx->stream_res.opp,
COLOR_SPACE_YCBCR601,
stream->timing.display_color_depth,
stream->signal);
}
}
}
void dc_stream_set_dither_option(struct dc_stream_state *stream,
enum dc_dither_option option)
{
struct bit_depth_reduction_params params;
struct dc_link *link = stream->link;
struct resource_context *res_ctx = &link->dc->current_state->res_ctx;
struct pipe_ctx *otg_master;
struct pipe_ctx *opp_heads[MAX_PIPES];
int opp_cnt;
int i;
otg_master = resource_get_otg_master_for_stream(res_ctx, stream);
if (!otg_master)
return;
if (option > DITHER_OPTION_MAX)
return;
opp_cnt = resource_get_opp_heads_for_otg_master(otg_master, res_ctx, opp_heads);
if (opp_cnt == 0)
return;
dc_exit_ips_for_hw_access(stream->ctx->dc);
stream->dither_option = option;
memset(¶ms, 0, sizeof(params));
resource_build_bit_depth_reduction_params(stream, ¶ms);
stream->bit_depth_params = params;
/*
* Program bit-depth reduction (dither) on every OPP head of the
* stream. Under ODM combine there is more than one OPP head and they
* must all be kept in sync, otherwise (e.g. when CRC capture requests
* dither off) a secondary ODM segment can keep dither enabled and
* produce a different CRC than the primary segment.
*/
for (i = 0; i < opp_cnt; i++) {
struct pipe_ctx *opp_head = opp_heads[i];
if (opp_head->plane_res.xfm &&
opp_head->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
opp_head->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
opp_head->plane_res.xfm,
opp_head->plane_res.scl_data.lb_params.depth,
&stream->bit_depth_params);
}
if (opp_head->stream_res.opp &&
opp_head->stream_res.opp->funcs->opp_program_bit_depth_reduction) {
opp_head->stream_res.opp->funcs->opp_program_bit_depth_reduction(
opp_head->stream_res.opp, ¶ms);
}
}
}
bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
{
int i;
bool ret = false;
struct pipe_ctx *pipes;
dc_exit_ips_for_hw_access(dc);
for (i = 0; i < MAX_PIPES; i++) {
if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
pipes = &dc->current_state->res_ctx.pipe_ctx[i];
dc->hwss.program_gamut_remap(&(struct program_gamut_remap_params) {
.xfm = pipes->plane_res.xfm,
.dpp = pipes->plane_res.dpp,
.mpc = dc->res_pool->mpc,
.mpcc_id = pipes->plane_res.mpcc_inst,
.stream = pipes->stream,
.plane = pipes->plane_state,
.is_top_pipe = pipes->top_pipe == NULL,
});
ret = true;
}
}
return ret;
}
bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
{
int i;
bool ret = false;
struct pipe_ctx *pipes;
dc_exit_ips_for_hw_access(dc);
for (i = 0; i < MAX_PIPES; i++) {
if (dc->current_state->res_ctx.pipe_ctx[i].stream
== stream) {
pipes = &dc->current_state->res_ctx.pipe_ctx[i];
dc->hwss.program_output_csc(dc,
pipes,
stream->output_color_space,
stream->csc_color_matrix.matrix,
pipes->stream_res.opp->inst);
ret = true;
}
}
return ret;
}
void dc_stream_set_static_screen_params(struct dc *dc,
struct dc_stream_state **streams,
int num_streams,
const struct dc_static_screen_params *params)
{
int i, j;
struct pipe_ctx *pipes_affected[MAX_PIPES];
int num_pipes_affected = 0;
dc_exit_ips_for_hw_access(dc);
for (i = 0; i < num_streams; i++) {
struct dc_stream_state *stream = streams[i];
for (j = 0; j < MAX_PIPES; j++) {
if (dc->current_state->res_ctx.pipe_ctx[j].stream
== stream) {
pipes_affected[num_pipes_affected++] =
&dc->current_state->res_ctx.pipe_ctx[j];
}
}
}
dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, params);
}
static void dc_destruct_update_scratch_pool(struct dc *dc)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(dc->update_scratch_pool); i++) {
kfree(dc->update_scratch_pool[i]);
dc->update_scratch_pool[i] = NULL;
dc->update_scratch_in_use[i] = false;
}
}
static bool dc_construct_update_scratch_pool(struct dc *dc)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(dc->update_scratch_pool); i++) {
dc->update_scratch_pool[i] = kzalloc(
sizeof(struct dc_update_scratch_space), GFP_KERNEL);
if (!dc->update_scratch_pool[i])
return false;
dc->update_scratch_in_use[i] = false;
}
return true;
}
static void dc_destruct(struct dc *dc)
{
// reset link encoder assignment table on destruct
if (dc->res_pool && dc->res_pool->funcs->link_encs_assign &&
!dc->config.unify_link_enc_assignment)
link_enc_cfg_init(dc, dc->current_state);
dc_destruct_update_scratch_pool(dc);
if (dc->current_state) {
dc_state_release(dc->current_state);
dc->current_state = NULL;
}
destroy_links(dc);
destroy_link_encoders(dc);
if (dc->clk_mgr) {
dc_destroy_clk_mgr(dc->clk_mgr);
dc->clk_mgr = NULL;
}
dc_destroy_resource_pool(dc);
#ifdef CONFIG_DRM_AMD_DC_FP
dc_destroy_soc_and_ip_translator(&dc->soc_and_ip_translator);
#endif
if (dc->link_srv)
link_destroy_link_service(&dc->link_srv);
if (dc->ctx) {
if (dc->ctx->gpio_service)
dal_gpio_service_destroy(&dc->ctx->gpio_service);
if (dc->ctx->created_bios)
dal_bios_parser_destroy(&dc->ctx->dc_bios);
kfree(dc->ctx->logger);
dc_perf_trace_destroy(&dc->ctx->perf_trace);
kfree(dc->ctx);
dc->ctx = NULL;
}
kfree(dc->bw_vbios);
dc->bw_vbios = NULL;
kfree(dc->bw_dceip);
dc->bw_dceip = NULL;
kfree(dc->dcn_soc);
dc->dcn_soc = NULL;
kfree(dc->dcn_ip);
dc->dcn_ip = NULL;
kfree(dc->vm_helper);
dc->vm_helper = NULL;
}
static bool dc_construct_ctx(struct dc *dc,
const struct dc_init_data *init_params)
{
struct dc_context *dc_ctx;
dc_ctx = kzalloc_obj(*dc_ctx);
if (!dc_ctx)
return false;
dc_stream_init_rmcm_3dlut(dc);
dc_ctx->cgs_device = init_params->cgs_device;
dc_ctx->driver_context = init_params->driver;
dc_ctx->dc = dc;
dc_ctx->asic_id = init_params->asic_id;
dc_ctx->dc_sink_id_count = 0;
dc_ctx->dc_stream_id_count = 0;
dc_ctx->dce_environment = init_params->dce_environment;
dc_ctx->dcn_reg_offsets = init_params->dcn_reg_offsets;
dc_ctx->nbio_reg_offsets = init_params->nbio_reg_offsets;
dc_ctx->clk_reg_offsets = init_params->clk_reg_offsets;
/* Create logger */
dc_ctx->logger = kmalloc_obj(*dc_ctx->logger);
if (!dc_ctx->logger) {
kfree(dc_ctx);
return false;
}
dc_ctx->logger->dev = adev_to_drm(init_params->driver);
dc->dml.logger = dc_ctx->logger;
dc_ctx->dce_version = resource_parse_asic_id(init_params->asic_id);
dc_ctx->perf_trace = dc_perf_trace_create();
if (!dc_ctx->perf_trace) {
kfree(dc_ctx);
ASSERT_CRITICAL(false);
return false;
}
dc->ctx = dc_ctx;
dc->link_srv = link_create_link_service();
if (!dc->link_srv)
return false;
return true;
}
static bool dc_construct(struct dc *dc,
const struct dc_init_data *init_params)
{
struct dc_context *dc_ctx;
struct bw_calcs_dceip *dc_dceip;
struct bw_calcs_vbios *dc_vbios;
struct dcn_soc_bounding_box *dcn_soc;
struct dcn_ip_params *dcn_ip;
dc->config = init_params->flags;
// Allocate memory for the vm_helper
dc->vm_helper = kzalloc_obj(struct vm_helper);
if (!dc->vm_helper) {
dm_error("%s: failed to create dc->vm_helper\n", __func__);
goto fail;
}
memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
dc_dceip = kzalloc_obj(*dc_dceip);
if (!dc_dceip) {
dm_error("%s: failed to create dceip\n", __func__);
goto fail;
}
dc->bw_dceip = dc_dceip;
dc_vbios = kzalloc_obj(*dc_vbios);
if (!dc_vbios) {
dm_error("%s: failed to create vbios\n", __func__);
goto fail;
}
dc->bw_vbios = dc_vbios;
dcn_soc = kzalloc_obj(*dcn_soc);
if (!dcn_soc) {
dm_error("%s: failed to create dcn_soc\n", __func__);
goto fail;
}
dc->dcn_soc = dcn_soc;
dcn_ip = kzalloc_obj(*dcn_ip);
if (!dcn_ip) {
dm_error("%s: failed to create dcn_ip\n", __func__);
goto fail;
}
dc->dcn_ip = dcn_ip;
if (init_params->bb_from_dmub)
dc->dml2_options.bb_from_dmub = init_params->bb_from_dmub;
else
dc->dml2_options.bb_from_dmub = NULL;
if (!dc_construct_ctx(dc, init_params)) {
dm_error("%s: failed to create ctx\n", __func__);
goto fail;
}
dc_ctx = dc->ctx;
/* Resource should construct all asic specific resources.
* This should be the only place where we need to parse the asic id
*/
if (init_params->vbios_override)
dc_ctx->dc_bios = init_params->vbios_override;
else {
/* Create BIOS parser */
struct bp_init_data bp_init_data;
bp_init_data.ctx = dc_ctx;
bp_init_data.bios = init_params->asic_id.atombios_base_address;
dc_ctx->dc_bios = dal_bios_parser_create(
&bp_init_data, dc_ctx->dce_version);
if (!dc_ctx->dc_bios) {
ASSERT_CRITICAL(false);
goto fail;
}
dc_ctx->created_bios = true;
}
dc->vendor_signature = init_params->vendor_signature;
/* Create GPIO service */
dc_ctx->gpio_service = dal_gpio_service_create(
dc_ctx->dce_version,
dc_ctx->dce_environment,
dc_ctx);
if (!dc_ctx->gpio_service) {
ASSERT_CRITICAL(false);
goto fail;
}
dc->res_pool = dc_create_resource_pool(dc, init_params, dc_ctx->dce_version);
if (!dc->res_pool)
goto fail;
/* set i2c speed if not done by the respective dcnxxx__resource.c */
if (dc->caps.i2c_speed_in_khz_hdcp == 0)
dc->caps.i2c_speed_in_khz_hdcp = dc->caps.i2c_speed_in_khz;
if (dc->check_config.max_optimizable_video_width == 0)
dc->check_config.max_optimizable_video_width = 5120;
dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
if (!dc->clk_mgr)
goto fail;
#ifdef CONFIG_DRM_AMD_DC_FP
dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;
if (dc->res_pool->funcs->update_bw_bounding_box)
dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
dc->soc_and_ip_translator = dc_create_soc_and_ip_translator(dc_ctx->dce_version);
if (!dc->soc_and_ip_translator)
goto fail;
#endif
if (!create_links(dc, init_params->num_virtual_links))
goto fail;
/* Create additional DIG link encoder objects if fewer than the platform
* supports were created during link construction.
*/
if (!create_link_encoders(dc))
goto fail;
/* Creation of current_state must occur after dc->dml
* is initialized in dc_create_resource_pool because
* on creation it copies the contents of dc->dml
*/
dc->current_state = dc_state_create(dc, NULL);
if (!dc->current_state) {
dm_error("%s: failed to create validate ctx\n", __func__);
goto fail;
}
if (!dc_construct_update_scratch_pool(dc)) {
dm_error("%s: failed to create update scratch pool\n", __func__);
goto fail;
}
return true;
fail:
return false;
}
static void disable_all_writeback_pipes_for_stream(
const struct dc *dc,
struct dc_stream_state *stream,
struct dc_state *context)
{
(void)dc;
(void)context;
unsigned int i;
for (i = 0; i < stream->num_wb_info; i++)
stream->writeback_info[i].wb_enabled = false;
}
static void apply_ctx_interdependent_lock(struct dc *dc,
struct dc_state *context,
struct dc_stream_state *stream,
bool lock)
{
(void)dc;
(void)context;
unsigned int i;
/* Checks if interdependent update function pointer is NULL or not, takes care of DCE110 case */
if (dc->hwss.interdependent_update_lock)
dc->hwss.interdependent_update_lock(dc, context, lock);
else {
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
// Copied conditions that were previously in dce110_apply_ctx_for_surface
if (stream == pipe_ctx->stream) {
if (resource_is_pipe_type(pipe_ctx, OPP_HEAD) &&
(pipe_ctx->plane_state || old_pipe_ctx->plane_state))
dc->hwss.pipe_control_lock(dc, pipe_ctx, lock);
}
}
}
}
static void dc_update_visual_confirm_color(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
{
if (dc->debug.visual_confirm & VISUAL_CONFIRM_EXPLICIT) {
memcpy(&pipe_ctx->visual_confirm_color, &pipe_ctx->plane_state->visual_confirm_color,
sizeof(pipe_ctx->visual_confirm_color));
return;
}
if (dc->ctx->dce_version >= DCN_VERSION_1_0) {
memset(&pipe_ctx->visual_confirm_color, 0, sizeof(struct tg_color));
if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)
get_hdr_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
get_surface_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)
get_surface_tile_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
else if (dc->debug.visual_confirm == VISUAL_CONFIRM_HW_CURSOR)
get_cursor_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
else if (dc->debug.visual_confirm == VISUAL_CONFIRM_DCC)
get_dcc_visual_confirm_color(dc, pipe_ctx, &(pipe_ctx->visual_confirm_color));
else {
if (dc->ctx->dce_version < DCN_VERSION_2_0)
color_space_to_black_color(
dc, pipe_ctx->stream->output_color_space, &(pipe_ctx->visual_confirm_color));
}
if (dc->ctx->dce_version >= DCN_VERSION_2_0) {
if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE)
get_mpctree_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP)
get_subvp_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MCLK_SWITCH)
get_mclk_switch_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
else if (dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS2)
get_fams2_visual_confirm_color(dc, context, pipe_ctx, &(pipe_ctx->visual_confirm_color));
else if (dc->debug.visual_confirm == VISUAL_CONFIRM_VABC)
get_vabc_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
else if (dc->debug.visual_confirm == VISUAL_CONFIRM_BOOSTED_REFRESH_RATE)
get_refresh_rate_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
}
}
}
void dc_get_visual_confirm_for_stream(
struct dc *dc,
struct dc_stream_state *stream_state,
struct tg_color *color)
{
struct dc_stream_status *stream_status = dc_stream_get_status(stream_state);
struct pipe_ctx *pipe_ctx;
int i;
struct dc_plane_state *plane_state = NULL;
if (!stream_status)
return;
switch (dc->debug.visual_confirm) {
case VISUAL_CONFIRM_DISABLE:
return;
case VISUAL_CONFIRM_PSR:
case VISUAL_CONFIRM_FAMS:
pipe_ctx = dc_stream_get_pipe_ctx(stream_state);
if (!pipe_ctx)
return;
dc_dmub_srv_get_visual_confirm_color_cmd(dc, pipe_ctx);
memcpy(color, &dc->ctx->dmub_srv->dmub->visual_confirm_color, sizeof(struct tg_color));
return;
default:
/* find plane with highest layer_index */
for (i = 0; i < stream_status->plane_count; i++) {
if (stream_status->plane_states[i]->visible)
plane_state = stream_status->plane_states[i];
}
if (!plane_state)
return;
/* find pipe that contains plane with highest layer index */
for (i = 0; i < MAX_PIPES; i++) {
struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
if (pipe->plane_state == plane_state) {
memcpy(color, &pipe->visual_confirm_color, sizeof(struct tg_color));
return;
}
}
}
}
/**
* dc_stream_adjust_vmin_vmax - look up pipe context & update parts of DRR
* @dc: dc reference
* @stream: Initial dc stream state
* @adjust: Updated parameters for vertical_total_min and vertical_total_max
*
* Looks up the pipe context of dc_stream_state and updates the
* vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
* Rate, which is a power-saving feature that targets reducing panel
* refresh rate while the screen is static
*
* Return: %true if the pipe context is found and adjusted;
* %false if the pipe context is not found.
*/
bool dc_stream_adjust_vmin_vmax(struct dc *dc,
struct dc_stream_state *stream,
struct dc_crtc_timing_adjust *adjust)
{
int i;
/*
* Don't adjust DRR while there's bandwidth optimizations pending to
* avoid conflicting with firmware updates.
*/
if (dc->ctx->dce_version > DCE_VERSION_MAX) {
if (dc->optimized_required &&
(stream->adjust.v_total_max != adjust->v_total_max ||
stream->adjust.v_total_min != adjust->v_total_min)) {
stream->adjust.timing_adjust_pending = true;
return false;
}
}
dc_exit_ips_for_hw_access(dc);
stream->adjust.v_total_max = adjust->v_total_max;
stream->adjust.v_total_mid = adjust->v_total_mid;
stream->adjust.v_total_mid_frame_num = adjust->v_total_mid_frame_num;
stream->adjust.v_total_min = adjust->v_total_min;
stream->adjust.allow_otg_v_count_halt = adjust->allow_otg_v_count_halt;
if (dc->caps.max_v_total != 0 &&
(adjust->v_total_max > dc->caps.max_v_total || adjust->v_total_min > dc->caps.max_v_total)) {
stream->adjust.timing_adjust_pending = false;
if (adjust->allow_otg_v_count_halt)
return set_long_vtotal(dc, stream, adjust);
else
return false;
}
for (i = 0; i < MAX_PIPES; i++) {
struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
if (pipe->stream == stream && pipe->stream_res.tg) {
dc->hwss.set_drr(&pipe,
1,
*adjust);
stream->adjust.timing_adjust_pending = false;
if (dc->debug.visual_confirm == VISUAL_CONFIRM_BOOSTED_REFRESH_RATE) {
if (pipe->stream && pipe->plane_state) {
dc_update_visual_confirm_color(dc, dc->current_state, pipe);
dc->hwss.update_visual_confirm_color(dc, pipe, pipe->plane_res.hubp->mpcc_id);
}
}
if (dc->hwss.notify_cursor_offload_drr_update)
dc->hwss.notify_cursor_offload_drr_update(dc, dc->current_state, stream);
return true;
}
}
return false;
}
static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
{
unsigned int i, j;
struct dc_state *dangling_context = dc_state_create_current_copy(dc);
struct dc_state *current_ctx;
struct pipe_ctx *pipe;
struct timing_generator *tg;
if (dangling_context == NULL)
return;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct dc_stream_state *old_stream =
dc->current_state->res_ctx.pipe_ctx[i].stream;
bool should_disable = true;
bool pipe_split_change = false;
if ((context->res_ctx.pipe_ctx[i].top_pipe) &&
(dc->current_state->res_ctx.pipe_ctx[i].top_pipe))
pipe_split_change = context->res_ctx.pipe_ctx[i].top_pipe->pipe_idx !=
dc->current_state->res_ctx.pipe_ctx[i].top_pipe->pipe_idx;
else
pipe_split_change = context->res_ctx.pipe_ctx[i].top_pipe !=
dc->current_state->res_ctx.pipe_ctx[i].top_pipe;
for (j = 0; j < context->stream_count; j++) {
if (old_stream == context->streams[j]) {
should_disable = false;
break;
}
}
if (!should_disable && pipe_split_change &&
dc->current_state->stream_count != context->stream_count)
should_disable = true;
if (old_stream && !dc->current_state->res_ctx.pipe_ctx[i].top_pipe &&
!dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe) {
struct pipe_ctx *old_pipe, *new_pipe;
old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
new_pipe = &context->res_ctx.pipe_ctx[i];
if (old_pipe->plane_state && !new_pipe->plane_state)
should_disable = true;
}
if (should_disable && old_stream) {
bool is_phantom = dc_state_get_stream_subvp_type(dc->current_state, old_stream) == SUBVP_PHANTOM;
pipe = &dc->current_state->res_ctx.pipe_ctx[i];
tg = pipe->stream_res.tg;
/* When disabling plane for a phantom pipe, we must turn on the
* phantom OTG so the disable programming gets the double buffer
* update. Otherwise the pipe will be left in a partially disabled
* state that can result in underflow or hang when enabling it
* again for different use.
*/
if (is_phantom) {
if (tg->funcs->enable_crtc) {
if (dc->hwseq->funcs.blank_pixel_data)
dc->hwseq->funcs.blank_pixel_data(dc, pipe, true);
tg->funcs->enable_crtc(tg);
}
}
if (is_phantom)
dc_state_rem_all_phantom_planes_for_stream(dc, old_stream, dangling_context, true);
else
dc_state_rem_all_planes_for_stream(dc, old_stream, dangling_context);
disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
if (pipe->stream && pipe->plane_state) {
if (!dc->debug.using_dml2)
set_p_state_switch_method(dc, context, pipe);
dc_update_visual_confirm_color(dc, context, pipe);
}
if (dc->hwss.apply_ctx_for_surface) {
apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, true);
dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, false);
dc->hwss.post_unlock_program_front_end(dc, dangling_context);
}
if (dc->res_pool->funcs->prepare_mcache_programming)
dc->res_pool->funcs->prepare_mcache_programming(dc, dangling_context);
if (dc->hwss.program_front_end_for_ctx) {
dc->hwss.interdependent_update_lock(dc, dc->current_state, true);
dc->hwss.program_front_end_for_ctx(dc, dangling_context);
dc->hwss.interdependent_update_lock(dc, dc->current_state, false);
dc->hwss.post_unlock_program_front_end(dc, dangling_context);
}
/* We need to put the phantom OTG back into it's default (disabled) state or we
* can get corruption when transition from one SubVP config to a different one.
* The OTG is set to disable on falling edge of VUPDATE so the plane disable
* will still get it's double buffer update.
*/
if (is_phantom) {
if (tg->funcs->disable_phantom_crtc)
tg->funcs->disable_phantom_crtc(tg);
}
}
}
current_ctx = dc->current_state;
dc->current_state = dangling_context;
dc_state_release(current_ctx);
}
static void disable_vbios_mode_if_required(
struct dc *dc,
struct dc_state *context)
{
unsigned int i, j;
/* check if timing_changed, disable stream*/
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct dc_stream_state *stream = NULL;
struct dc_link *link = NULL;
struct pipe_ctx *pipe = NULL;
pipe = &context->res_ctx.pipe_ctx[i];
stream = pipe->stream;
if (stream == NULL)
continue;
if (stream->apply_seamless_boot_optimization)
continue;
// only looking for first odm pipe
if (pipe->prev_odm_pipe)
continue;
if (stream->link->local_sink &&
stream->link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
link = stream->link;
}
if (link != NULL && link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
unsigned int enc_inst, tg_inst = 0;
unsigned int pix_clk_100hz = 0;
enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
if (enc_inst != ENGINE_ID_UNKNOWN) {
for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
if (dc->res_pool->stream_enc[j]->id == enc_inst) {
tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg(
dc->res_pool->stream_enc[j]);
break;
}
}
dc->res_pool->dp_clock_source->funcs->get_dp_dto_frequency_100hz(
dc->res_pool->dp_clock_source,
tg_inst, &pix_clk_100hz);
if (link->link_status.link_active) {
uint32_t requested_pix_clk_100hz =
pipe->stream_res.pix_clk_params.requested_pix_clk_100hz;
if (pix_clk_100hz != requested_pix_clk_100hz) {
dc->link_srv->set_dpms_off(pipe);
pipe->stream->dpms_off = false;
}
}
}
}
}
}
/* Public functions */
struct dc *dc_create(const struct dc_init_data *init_params)
{
struct dc *dc = kvzalloc_obj(*dc);
unsigned int full_pipe_count;
if (!dc)
return NULL;
if (init_params->dce_environment == DCE_ENV_VIRTUAL_HW) {
dc->caps.linear_pitch_alignment = 64;
if (!dc_construct_ctx(dc, init_params))
goto destruct_dc;
} else {
if (!dc_construct(dc, init_params))
goto destruct_dc;
full_pipe_count = dc->res_pool->pipe_count;
if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
full_pipe_count--;
dc->caps.max_streams = min(
full_pipe_count,
dc->res_pool->stream_enc_count);
dc->caps.max_links = dc->link_count;
dc->caps.max_audios = dc->res_pool->audio_count;
dc->caps.linear_pitch_alignment = 64;
dc->caps.max_dp_protocol_version = DP_VERSION_1_4;
dc->caps.max_otg_num = dc->res_pool->res_cap->num_timing_generator;
if (dc->res_pool->dmcu != NULL)
dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
}
dc->dcn_reg_offsets = init_params->dcn_reg_offsets;
dc->nbio_reg_offsets = init_params->nbio_reg_offsets;
dc->clk_reg_offsets = init_params->clk_reg_offsets;
/* Populate versioning information */
dc->versions.dc_ver = DC_VER;
dc->build_id = DC_BUILD_ID;
DC_LOG_DC("Display Core initialized\n");
return dc;
destruct_dc:
dc_destruct(dc);
kvfree(dc);
return NULL;
}
static void detect_edp_presence(struct dc *dc)
{
struct dc_link *edp_links[MAX_NUM_EDP];
struct dc_link *edp_link = NULL;
enum dc_connection_type type;
unsigned int i, edp_num;
dc_get_edp_links(dc, edp_links, &edp_num);
if (!edp_num)
return;
for (i = 0; i < edp_num; i++) {
edp_link = edp_links[i];
if (dc->config.edp_not_connected) {
edp_link->edp_sink_present = false;
} else {
dc_link_detect_connection_type(edp_link, &type);
edp_link->edp_sink_present = (type != dc_connection_none);
}
}
}
void dc_hardware_init(struct dc *dc)
{
detect_edp_presence(dc);
if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW)
dc->hwss.init_hw(dc);
dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);
}
void dc_init_callbacks(struct dc *dc,
const struct dc_callback_init *init_params)
{
dc->ctx->cp_psp = init_params->cp_psp;
}
void dc_deinit_callbacks(struct dc *dc)
{
memset(&dc->ctx->cp_psp, 0, sizeof(dc->ctx->cp_psp));
}
void dc_destroy(struct dc **dc)
{
dc_destruct(*dc);
kvfree(*dc);
*dc = NULL;
}
static void enable_timing_multisync(
struct dc *dc,
struct dc_state *ctx)
{
int i, multisync_count = 0;
int pipe_count = dc->res_pool->pipe_count;
struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
for (i = 0; i < pipe_count; i++) {
if (!ctx->res_ctx.pipe_ctx[i].stream ||
!ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)
continue;
if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)
continue;
multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];
multisync_count++;
}
if (multisync_count > 0) {
dc->hwss.enable_per_frame_crtc_position_reset(
dc, multisync_count, multisync_pipes);
}
}
static void program_timing_sync(
struct dc *dc,
struct dc_state *ctx)
{
int i, j, k;
int group_index = 0;
int num_group = 0;
int pipe_count = dc->res_pool->pipe_count;
struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
for (i = 0; i < pipe_count; i++) {
if (!ctx->res_ctx.pipe_ctx[i].stream
|| ctx->res_ctx.pipe_ctx[i].top_pipe
|| ctx->res_ctx.pipe_ctx[i].prev_odm_pipe)
continue;
unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
}
for (i = 0; i < pipe_count; i++) {
int group_size = 1;
enum timing_synchronization_type sync_type = NOT_SYNCHRONIZABLE;
struct pipe_ctx *pipe_set[MAX_PIPES];
if (!unsynced_pipes[i])
continue;
pipe_set[0] = unsynced_pipes[i];
unsynced_pipes[i] = NULL;
/* Add tg to the set, search rest of the tg's for ones with
* same timing, add all tgs with same timing to the group
*/
for (j = i + 1; j < pipe_count; j++) {
if (!unsynced_pipes[j])
continue;
if (sync_type != TIMING_SYNCHRONIZABLE &&
dc->hwss.enable_vblanks_synchronization &&
unsynced_pipes[j]->stream_res.tg->funcs->align_vblanks &&
resource_are_vblanks_synchronizable(
unsynced_pipes[j]->stream,
pipe_set[0]->stream)) {
sync_type = VBLANK_SYNCHRONIZABLE;
pipe_set[group_size] = unsynced_pipes[j];
unsynced_pipes[j] = NULL;
group_size++;
} else
if (sync_type != VBLANK_SYNCHRONIZABLE &&
resource_are_streams_timing_synchronizable(
unsynced_pipes[j]->stream,
pipe_set[0]->stream)) {
sync_type = TIMING_SYNCHRONIZABLE;
pipe_set[group_size] = unsynced_pipes[j];
unsynced_pipes[j] = NULL;
group_size++;
}
}
/* set first unblanked pipe as master */
for (j = 0; j < group_size; j++) {
bool is_blanked;
if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
is_blanked =
pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
else
is_blanked =
pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
if (!is_blanked) {
if (j == 0)
break;
swap(pipe_set[0], pipe_set[j]);
break;
}
}
for (k = 0; k < group_size; k++) {
struct dc_stream_status *status = dc_state_get_stream_status(ctx, pipe_set[k]->stream);
if (!status)
continue;
status->timing_sync_info.group_id = num_group;
status->timing_sync_info.group_size = group_size;
if (k == 0)
status->timing_sync_info.master = true;
else
status->timing_sync_info.master = false;
}
/* remove any other unblanked pipes as they have already been synced */
if (dc->config.use_pipe_ctx_sync_logic) {
/* check pipe's syncd to decide which pipe to be removed */
for (j = 1; j < group_size; j++) {
if (pipe_set[j]->pipe_idx_syncd == pipe_set[0]->pipe_idx_syncd) {
group_size--;
pipe_set[j] = pipe_set[group_size];
j--;
} else
/* link slave pipe's syncd with master pipe */
pipe_set[j]->pipe_idx_syncd = pipe_set[0]->pipe_idx_syncd;
}
} else {
/* remove any other pipes by checking valid plane */
for (j = j + 1; j < group_size; j++) {
bool is_blanked;
if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
is_blanked =
pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
else
is_blanked =
pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
if (!is_blanked) {
group_size--;
pipe_set[j] = pipe_set[group_size];
j--;
}
}
}
if (group_size > 1) {
if (sync_type == TIMING_SYNCHRONIZABLE) {
dc->hwss.enable_timing_synchronization(
dc, ctx, group_index, group_size, pipe_set);
} else
if (sync_type == VBLANK_SYNCHRONIZABLE) {
dc->hwss.enable_vblanks_synchronization(
dc, group_index, group_size, pipe_set);
}
group_index++;
}
num_group++;
}
}
static bool streams_changed(struct dc *dc,
struct dc_stream_state *streams[],
uint8_t stream_count)
{
uint8_t i;
if (stream_count != dc->current_state->stream_count)
return true;
for (i = 0; i < dc->current_state->stream_count; i++) {
if (dc->current_state->streams[i] != streams[i])
return true;
if (!streams[i]->link->link_state_valid)
return true;
}
return false;
}
bool dc_validate_boot_timing(const struct dc *dc,
const struct dc_sink *sink,
struct dc_crtc_timing *crtc_timing)
{
struct timing_generator *tg;
struct stream_encoder *se = NULL;
struct dc_crtc_timing hw_crtc_timing = {0};
struct dc_link *link = sink->link;
unsigned int i, enc_inst;
unsigned int tg_inst = 0;
/* Support seamless boot on EDP displays only */
if (sink->sink_signal != SIGNAL_TYPE_EDP) {
return false;
}
if (dc->debug.force_odm_combine) {
DC_LOG_DEBUG("boot timing validation failed due to force_odm_combine\n");
return false;
}
/* Check for enabled DIG to identify enabled display */
if (!link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
DC_LOG_DEBUG("boot timing validation failed due to disabled DIG\n");
return false;
}
enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
if (enc_inst == ENGINE_ID_UNKNOWN) {
DC_LOG_DEBUG("boot timing validation failed due to unknown DIG engine ID\n");
return false;
}
for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
if (dc->res_pool->stream_enc[i]->id == enc_inst) {
se = dc->res_pool->stream_enc[i];
tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(
dc->res_pool->stream_enc[i]);
break;
}
}
// tg_inst not found
if (i == dc->res_pool->stream_enc_count) {
DC_LOG_DEBUG("boot timing validation failed due to timing generator instance not found\n");
return false;
}
if (tg_inst >= dc->res_pool->timing_generator_count) {
DC_LOG_DEBUG("boot timing validation failed due to invalid timing generator count\n");
return false;
}
if (tg_inst != link->link_enc->preferred_engine) {
DC_LOG_DEBUG("boot timing validation failed due to non-preferred timing generator\n");
return false;
}
tg = dc->res_pool->timing_generators[tg_inst];
if (!tg->funcs->get_hw_timing) {
DC_LOG_DEBUG("boot timing validation failed due to missing get_hw_timing callback\n");
return false;
}
if (!tg->funcs->get_hw_timing(tg, &hw_crtc_timing)) {
DC_LOG_DEBUG("boot timing validation failed due to failed get_hw_timing return\n");
return false;
}
if (crtc_timing->h_total != hw_crtc_timing.h_total) {
DC_LOG_DEBUG("boot timing validation failed due to h_total mismatch\n");
return false;
}
if (crtc_timing->h_border_left != hw_crtc_timing.h_border_left) {
DC_LOG_DEBUG("boot timing validation failed due to h_border_left mismatch\n");
return false;
}
if (crtc_timing->h_addressable != hw_crtc_timing.h_addressable) {
DC_LOG_DEBUG("boot timing validation failed due to h_addressable mismatch\n");
return false;
}
if (crtc_timing->h_border_right != hw_crtc_timing.h_border_right) {
DC_LOG_DEBUG("boot timing validation failed due to h_border_right mismatch\n");
return false;
}
if (crtc_timing->h_front_porch != hw_crtc_timing.h_front_porch) {
DC_LOG_DEBUG("boot timing validation failed due to h_front_porch mismatch\n");
return false;
}
if (crtc_timing->h_sync_width != hw_crtc_timing.h_sync_width) {
DC_LOG_DEBUG("boot timing validation failed due to h_sync_width mismatch\n");
return false;
}
if (crtc_timing->v_total != hw_crtc_timing.v_total) {
DC_LOG_DEBUG("boot timing validation failed due to v_total mismatch\n");
return false;
}
if (crtc_timing->v_border_top != hw_crtc_timing.v_border_top) {
DC_LOG_DEBUG("boot timing validation failed due to v_border_top mismatch\n");
return false;
}
if (crtc_timing->v_addressable != hw_crtc_timing.v_addressable) {
DC_LOG_DEBUG("boot timing validation failed due to v_addressable mismatch\n");
return false;
}
if (crtc_timing->v_border_bottom != hw_crtc_timing.v_border_bottom) {
DC_LOG_DEBUG("boot timing validation failed due to v_border_bottom mismatch\n");
return false;
}
if (crtc_timing->v_front_porch != hw_crtc_timing.v_front_porch) {
DC_LOG_DEBUG("boot timing validation failed due to v_front_porch mismatch\n");
return false;
}
if (crtc_timing->v_sync_width != hw_crtc_timing.v_sync_width) {
DC_LOG_DEBUG("boot timing validation failed due to v_sync_width mismatch\n");
return false;
}
if (crtc_timing->flags.DSC) {
struct display_stream_compressor *dsc = NULL;
struct dcn_dsc_state dsc_state = {0};
if (dc->ctx->dce_version < DCN_VERSION_4_2) {
/*vbios enabled eDP dsc for one of DCN315 only but it has known issue,
since there is no production bios update, block it there*/
DC_LOG_DEBUG("boot timing validation failed due to unsupported DSC on this ASIC\n");
return false;
}
/* Find DSC associated with this timing generator */
if (tg_inst < (unsigned int)dc->res_pool->res_cap->num_dsc) {
dsc = dc->res_pool->dscs[tg_inst];
}
if (!dsc || !dsc->funcs->dsc_read_state) {
DC_LOG_DEBUG("boot timing validation failed due to no DSC resource or read function\n");
return false;
}
/* Read current DSC hardware state */
dsc->funcs->dsc_read_state(dsc, &dsc_state);
/* Check if DSC is actually enabled in hardware */
if (dsc_state.dsc_clock_en == 0) {
DC_LOG_DEBUG("boot timing validation failed due to DSC not enabled in hardware\n");
return false;
}
uint32_t num_slices_h = 0;
uint32_t num_slices_v = 0;
if (dsc_state.dsc_slice_width > 0) {
num_slices_h = (crtc_timing->h_addressable + dsc_state.dsc_slice_width - 1) / dsc_state.dsc_slice_width;
}
if (dsc_state.dsc_slice_height > 0) {
num_slices_v = (crtc_timing->v_addressable + dsc_state.dsc_slice_height - 1) / dsc_state.dsc_slice_height;
}
if (crtc_timing->dsc_cfg.num_slices_h != num_slices_h) {
DC_LOG_DEBUG("boot timing validation failed due to num_slices_h mismatch\n");
return false;
}
if (crtc_timing->dsc_cfg.num_slices_v != num_slices_v) {
DC_LOG_DEBUG("boot timing validation failed due to num_slices_v mismatch\n");
return false;
}
if (crtc_timing->dsc_cfg.bits_per_pixel != dsc_state.dsc_bits_per_pixel) {
DC_LOG_DEBUG("boot timing validation failed due to bits_per_pixel mismatch\n");
return false;
}
if (crtc_timing->dsc_cfg.block_pred_enable != dsc_state.dsc_block_pred_enable) {
DC_LOG_DEBUG("boot timing validation failed due to block_pred_enable mismatch\n");
return false;
}
if (crtc_timing->dsc_cfg.linebuf_depth != dsc_state.dsc_line_buf_depth) {
DC_LOG_DEBUG("boot timing validation failed due to linebuf_depth mismatch\n");
return false;
}
if (crtc_timing->dsc_cfg.version_minor != dsc_state.dsc_version_minor) {
DC_LOG_DEBUG("boot timing validation failed due to version_minor mismatch\n");
return false;
}
if (crtc_timing->dsc_cfg.ycbcr422_simple != dsc_state.dsc_simple_422) {
DC_LOG_DEBUG("boot timing validation failed due to pixel encoding mismatch\n");
return false;
}
// Skip checks for is_frl, is_dp, and rc_buffer_size which are not programmed by vbios
// or not necessary for seamless boot validation.
}
if (dc_is_dp_signal(link->connector_signal)) {
unsigned int pix_clk_100hz = 0;
uint32_t numOdmPipes = 1;
uint32_t id_src[4] = {0};
dc->res_pool->dp_clock_source->funcs->get_dp_dto_frequency_100hz(
dc->res_pool->dp_clock_source,
tg_inst, &pix_clk_100hz);
if (tg->funcs->get_optc_source)
tg->funcs->get_optc_source(tg,
&numOdmPipes, &id_src[0], &id_src[1]);
if (numOdmPipes == 2) {
pix_clk_100hz *= 2;
} else if (numOdmPipes == 4) {
pix_clk_100hz *= 4;
} else if (se && se->funcs->get_pixels_per_cycle) {
uint32_t pixels_per_cycle = se->funcs->get_pixels_per_cycle(se);
if (pixels_per_cycle != 1 && !dc->debug.enable_dp_dig_pixel_rate_div_policy) {
DC_LOG_DEBUG("boot timing validation failed due to pixels_per_cycle\n");
return false;
}
pix_clk_100hz *= pixels_per_cycle;
}
// Note: In rare cases, HW pixclk may differ from crtc's pixclk
// slightly due to rounding issues in 10 kHz units.
if (crtc_timing->pix_clk_100hz != pix_clk_100hz) {
DC_LOG_DEBUG("boot timing validation failed due to pix_clk_100hz mismatch\n");
return false;
}
if (!se || !se->funcs->dp_get_pixel_format) {
DC_LOG_DEBUG("boot timing validation failed due to missing dp_get_pixel_format\n");
return false;
}
if (!se->funcs->dp_get_pixel_format(
se,
&hw_crtc_timing.pixel_encoding,
&hw_crtc_timing.display_color_depth)) {
DC_LOG_DEBUG("boot timing validation failed due to dp_get_pixel_format failure\n");
return false;
}
if (hw_crtc_timing.display_color_depth != crtc_timing->display_color_depth) {
DC_LOG_DEBUG("boot timing validation failed due to display_color_depth mismatch\n");
return false;
}
if (hw_crtc_timing.pixel_encoding != crtc_timing->pixel_encoding) {
DC_LOG_DEBUG("boot timing validation failed due to pixel_encoding mismatch\n");
return false;
}
}
if (link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) {
DC_LOG_DEBUG("boot timing validation failed due to VSC SDP colorimetry\n");
return false;
}
if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) {
DC_LOG_DEBUG("boot timing validation failed due to DP 128b/132b\n");
return false;
}
if (dc->link_srv->edp_is_ilr_optimization_required(link, crtc_timing)) {
DC_LOG_EVENT_LINK_TRAINING("Seamless boot disabled to optimize eDP link rate\n");
return false;
}
return true;
}
static inline bool should_update_pipe_for_stream(
struct dc_state *context,
struct pipe_ctx *pipe_ctx,
struct dc_stream_state *stream)
{
return (pipe_ctx->stream && pipe_ctx->stream == stream);
}
static inline bool should_update_pipe_for_plane(
struct dc_state *context,
struct pipe_ctx *pipe_ctx,
struct dc_plane_state *plane_state)
{
return (pipe_ctx->plane_state == plane_state);
}
void dc_enable_stereo(
struct dc *dc,
struct dc_state *context,
struct dc_stream_state *streams[],
uint8_t stream_count)
{
int i, j;
struct pipe_ctx *pipe;
dc_exit_ips_for_hw_access(dc);
for (i = 0; i < MAX_PIPES; i++) {
if (context != NULL) {
pipe = &context->res_ctx.pipe_ctx[i];
} else {
context = dc->current_state;
pipe = &dc->current_state->res_ctx.pipe_ctx[i];
}
for (j = 0; pipe && j < stream_count; j++) {
if (should_update_pipe_for_stream(context, pipe, streams[j]) &&
dc->hwss.setup_stereo)
dc->hwss.setup_stereo(pipe, dc);
}
}
}
void dc_trigger_sync(struct dc *dc, struct dc_state *context)
{
if (context->stream_count > 1 && !dc->debug.disable_timing_sync) {
dc_exit_ips_for_hw_access(dc);
enable_timing_multisync(dc, context);
program_timing_sync(dc, context);
}
}
static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)
{
unsigned int i;
unsigned int stream_mask = 0;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
if (context->res_ctx.pipe_ctx[i].stream)
stream_mask |= 1 << i;
}
return (uint8_t)stream_mask;
}
void dc_z10_restore(const struct dc *dc)
{
if (dc->hwss.z10_restore)
dc->hwss.z10_restore(dc);
}
void dc_z10_save_init(struct dc *dc)
{
if (dc->hwss.z10_save_init)
dc->hwss.z10_save_init(dc);
}
/* Set a pipe unlock order based on the change in DET allocation and stores it in dc scratch memory
* Prevents over allocation of DET during unlock process
* e.g. 2 pipe config with different streams with a max of 20 DET segments
* Before: After:
* - Pipe0: 10 DET segments - Pipe0: 12 DET segments
* - Pipe1: 10 DET segments - Pipe1: 8 DET segments
* If Pipe0 gets updated first, 22 DET segments will be allocated
*/
static void determine_pipe_unlock_order(struct dc *dc, struct dc_state *context)
{
unsigned int i = 0;
struct pipe_ctx *pipe = NULL;
struct timing_generator *tg = NULL;
if (!dc->config.set_pipe_unlock_order)
return;
memset(dc->scratch.pipes_to_unlock_first, 0, sizeof(dc->scratch.pipes_to_unlock_first));
for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe = &context->res_ctx.pipe_ctx[i];
tg = pipe->stream_res.tg;
if (!resource_is_pipe_type(pipe, OTG_MASTER) ||
!tg->funcs->is_tg_enabled(tg) ||
dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {
continue;
}
if (resource_calculate_det_for_stream(context, pipe) <
resource_calculate_det_for_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i])) {
dc->scratch.pipes_to_unlock_first[i] = true;
}
}
}
/**
* dc_commit_state_no_check - Apply context to the hardware
*
* @dc: DC object with the current status to be updated
* @context: New state that will become the current status at the end of this function
*
* Applies given context to the hardware and copy it into current context.
* It's up to the user to release the src context afterwards.
*
* Return: an enum dc_status result code for the operation
*/
static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
{
struct dc_bios *dcb = dc->ctx->dc_bios;
enum dc_status result = DC_ERROR_UNEXPECTED;
struct pipe_ctx *pipe;
unsigned int i, k, l;
struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
struct dc_state *old_state;
bool subvp_prev_use = false;
dc_z10_restore(dc);
dc_allow_idle_optimizations(dc, false);
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
/* Check old context for SubVP */
subvp_prev_use |= (dc_state_get_pipe_subvp_type(dc->current_state, old_pipe) == SUBVP_PHANTOM);
if (subvp_prev_use)
break;
}
for (i = 0; i < context->stream_count; i++)
dc_streams[i] = context->streams[i];
if (!dcb->funcs->is_accelerated_mode(dcb)) {
disable_vbios_mode_if_required(dc, context);
dc->hwss.enable_accelerated_mode(dc, context);
} else if (get_seamless_boot_stream_count(dc->current_state) > 0) {
/* If the previous Stream still retains the apply seamless boot flag,
* it means the OS has not actually performed a flip yet.
* At this point, if we receive dc_commit_streams again, we should
* once more check whether the actual HW timing matches what the OS
* has provided
*/
disable_vbios_mode_if_required(dc, context);
}
if (dc->hwseq->funcs.wait_for_pipe_update_if_needed) {
for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe = &context->res_ctx.pipe_ctx[i];
//Only delay otg master for a given config
if (resource_is_pipe_type(pipe, OTG_MASTER)) {
//dc_commit_state_no_check is always a full update
dc->hwseq->funcs.wait_for_pipe_update_if_needed(dc, pipe, false);
break;
}
}
}
if (context->stream_count > get_seamless_boot_stream_count(context) ||
context->stream_count == 0)
dc->hwss.prepare_bandwidth(dc, context);
/* When SubVP is active, all HW programming must be done while
* SubVP lock is acquired
*/
if (dc->hwss.subvp_pipe_control_lock)
dc->hwss.subvp_pipe_control_lock(dc, context, true, true, NULL, subvp_prev_use);
if (dc->hwss.dmub_hw_control_lock)
dc->hwss.dmub_hw_control_lock(dc, context, true);
if (dc->hwss.update_dsc_pg)
dc->hwss.update_dsc_pg(dc, context, false);
disable_dangling_plane(dc, context);
/* re-program planes for existing stream, in case we need to
* free up plane resource for later use
*/
if (dc->hwss.apply_ctx_for_surface) {
for (i = 0; i < context->stream_count; i++) {
if (context->streams[i]->mode_changed)
continue;
apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
dc->hwss.apply_ctx_for_surface(
dc, context->streams[i],
context->stream_status[i].plane_count,
context); /* use new pipe config in new context */
apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
dc->hwss.post_unlock_program_front_end(dc, context);
}
}
/* Program hardware */
for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe = &context->res_ctx.pipe_ctx[i];
dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
}
for (i = 0; i < dc->current_state->stream_count; i++)
dc_dmub_srv_control_cursor_offload(dc, dc->current_state, dc->current_state->streams[i], false);
result = dc->hwss.apply_ctx_to_hw(dc, context);
for (i = 0; i < context->stream_count; i++)
dc_dmub_srv_control_cursor_offload(dc, context, context->streams[i], true);
if (result != DC_OK) {
/* Application of dc_state to hardware stopped. */
dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_STEADY;
return result;
}
dc_trigger_sync(dc, context);
/* Full update should unconditionally be triggered when dc_commit_state_no_check is called */
for (i = 0; i < context->stream_count; i++) {
uint32_t prev_dsc_changed = context->streams[i]->update_flags.bits.dsc_changed;
stream_update_flags_set_full(&context->streams[i]->update_flags);
context->streams[i]->update_flags.bits.dsc_changed = prev_dsc_changed;
}
determine_pipe_unlock_order(dc, context);
/* Program all planes within new context*/
if (dc->res_pool->funcs->prepare_mcache_programming)
dc->res_pool->funcs->prepare_mcache_programming(dc, context);
if (dc->hwss.program_front_end_for_ctx) {
dc->hwss.interdependent_update_lock(dc, context, true);
dc->hwss.program_front_end_for_ctx(dc, context);
if (dc->hwseq->funcs.set_wait_for_update_needed_for_pipe) {
for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe = &context->res_ctx.pipe_ctx[i];
dc->hwseq->funcs.set_wait_for_update_needed_for_pipe(dc, pipe);
}
}
dc->hwss.interdependent_update_lock(dc, context, false);
dc->hwss.post_unlock_program_front_end(dc, context);
}
if (dc->hwss.commit_subvp_config)
dc->hwss.commit_subvp_config(dc, context);
if (dc->hwss.subvp_pipe_control_lock)
dc->hwss.subvp_pipe_control_lock(dc, context, false, true, NULL, subvp_prev_use);
if (dc->hwss.dmub_hw_control_lock)
dc->hwss.dmub_hw_control_lock(dc, context, false);
for (i = 0; i < context->stream_count; i++) {
const struct dc_link *link = context->streams[i]->link;
if (!context->streams[i]->mode_changed)
continue;
if (dc->hwss.apply_ctx_for_surface) {
apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
dc->hwss.apply_ctx_for_surface(
dc, context->streams[i],
context->stream_status[i].plane_count,
context);
apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
dc->hwss.post_unlock_program_front_end(dc, context);
}
/*
* enable stereo
* TODO rework dc_enable_stereo call to work with validation sets?
*/
for (k = 0; k < MAX_PIPES; k++) {
pipe = &context->res_ctx.pipe_ctx[k];
for (l = 0 ; pipe && l < context->stream_count; l++) {
if (context->streams[l] &&
context->streams[l] == pipe->stream &&
dc->hwss.setup_stereo)
dc->hwss.setup_stereo(pipe, dc);
}
}
CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",
context->streams[i]->timing.h_addressable,
context->streams[i]->timing.v_addressable,
context->streams[i]->timing.h_total,
context->streams[i]->timing.v_total,
context->streams[i]->timing.pix_clk_100hz / 10);
}
dc_enable_stereo(dc, context, dc_streams, context->stream_count);
if (get_seamless_boot_stream_count(context) == 0 ||
context->stream_count == 0) {
/* Must wait for no flips to be pending before doing optimize bw */
hwss_wait_for_no_pipes_pending(dc, context);
/*
* optimized dispclk depends on ODM setup. Need to wait for ODM
* update pending complete before optimizing bandwidth.
*/
hwss_wait_for_odm_update_pending_complete(dc, context);
/* pplib is notified if disp_num changed */
dc->hwss.optimize_bandwidth(dc, context);
/* Need to do otg sync again as otg could be out of sync due to otg
* workaround applied during clock update
*/
dc_trigger_sync(dc, context);
}
if (dc->hwss.update_dsc_pg)
dc->hwss.update_dsc_pg(dc, context, true);
if (dc->ctx->dce_version >= DCE_VERSION_MAX)
TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
else
TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
context->stream_mask = get_stream_mask(dc, context);
if (context->stream_mask != dc->current_state->stream_mask)
dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, context->stream_mask);
for (i = 0; i < context->stream_count; i++)
context->streams[i]->mode_changed = false;
/* Clear update flags that were set earlier to avoid redundant programming */
for (i = 0; i < context->stream_count; i++) {
stream_update_flags_clear(&context->streams[i]->update_flags);
}
old_state = dc->current_state;
dc->current_state = context;
dc_state_release(old_state);
dc_state_retain(dc->current_state);
return result;
}
static bool commit_minimal_transition_state(struct dc *dc,
struct dc_state *transition_base_context);
/**
* dc_commit_streams - Commit current stream state
*
* @dc: DC object with the commit state to be configured in the hardware
* @params: Parameters for the commit, including the streams to be committed
*
* Function responsible for commit streams change to the hardware.
*
* Return:
* Return DC_OK if everything work as expected, otherwise, return a dc_status
* code.
*/
enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params)
{
unsigned int i, j;
struct dc_state *context;
enum dc_status res = DC_OK;
struct dc_validation_set set = {0};
struct pipe_ctx *pipe;
bool handle_exit_odm2to1 = false;
if (!params)
return DC_ERROR_UNEXPECTED;
if (dc->ctx->dce_environment == DCE_ENV_VIRTUAL_HW)
return res;
if (!streams_changed(dc, params->streams, params->stream_count) &&
dc->current_state->power_source == params->power_source)
return res;
dc_exit_ips_for_hw_access(dc);
DC_LOG_DC("%s: %d streams\n", __func__, params->stream_count);
for (i = 0; i < params->stream_count; i++) {
struct dc_stream_state *stream = params->streams[i];
struct dc_stream_status *status = dc_stream_get_status(stream);
struct dc_sink *sink = stream->sink;
/* revalidate streams */
if (!dc_is_virtual_signal(sink->sink_signal)) {
res = dc_validate_stream(dc, stream);
if (res != DC_OK)
return res;
}
dc_stream_log(dc, stream);
set.streams[i].stream = stream;
if (status) {
set.streams[i].plane_count = (uint8_t)status->plane_count;
for (j = 0; j < (unsigned int)status->plane_count; j++)
set.streams[i].plane_states[j] = status->plane_states[j];
}
}
set.stream_count = (uint8_t)params->stream_count;
/* ODM Combine 2:1 power optimization is only applied for single stream
* scenario, it uses extra pipes than needed to reduce power consumption
* We need to switch off this feature to make room for new streams.
*/
if (params->stream_count > dc->current_state->stream_count &&
dc->current_state->stream_count == 1) {
for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe = &dc->current_state->res_ctx.pipe_ctx[i];
if (pipe->next_odm_pipe)
handle_exit_odm2to1 = true;
}
}
if (handle_exit_odm2to1)
res = commit_minimal_transition_state(dc, dc->current_state);
context = dc_state_create_current_copy(dc);
if (!context)
goto context_alloc_fail;
context->power_source = params->power_source;
res = dc_validate_with_context(dc, &set, context, DC_VALIDATE_MODE_AND_PROGRAMMING);
/*
* Only update link encoder to stream assignment after bandwidth validation passed.
*/
if (res == DC_OK && dc->res_pool->funcs->link_encs_assign && !dc->config.unify_link_enc_assignment)
dc->res_pool->funcs->link_encs_assign(
dc, context, context->streams, context->stream_count);
if (res != DC_OK) {
BREAK_TO_DEBUGGER();
goto fail;
}
/*
* If not already seamless, make transition seamless by inserting intermediate minimal transition
*/
if (dc->hwss.is_pipe_topology_transition_seamless &&
!dc->hwss.is_pipe_topology_transition_seamless(dc, dc->current_state, context)) {
res = commit_minimal_transition_state(dc, context);
if (res != DC_OK) {
BREAK_TO_DEBUGGER();
goto fail;
}
}
res = dc_commit_state_no_check(dc, context);
for (i = 0; i < params->stream_count; i++) {
for (j = 0; j < context->stream_count; j++) {
if (params->streams[i]->stream_id == context->streams[j]->stream_id)
params->streams[i]->out.otg_offset = (uint8_t)context->stream_status[j].primary_otg_inst;
if (dc_is_embedded_signal(params->streams[i]->signal)) {
struct dc_stream_status *status = dc_state_get_stream_status(context, params->streams[i]);
if (!status)
continue;
if (dc->hwss.is_abm_supported)
status->is_abm_supported = dc->hwss.is_abm_supported(dc, context, params->streams[i]);
else
status->is_abm_supported = true;
}
}
}
fail:
dc_state_release(context);
context_alloc_fail:
DC_LOG_DC("%s Finished.\n", __func__);
return res;
}
bool dc_acquire_release_mpc_3dlut(
struct dc *dc, bool acquire,
struct dc_stream_state *stream,
struct dc_3dlut **lut,
struct dc_transfer_func **shaper)
{
unsigned int pipe_idx;
bool ret = false;
bool found_pipe_idx = false;
const struct resource_pool *pool = dc->res_pool;
struct resource_context *res_ctx = &dc->current_state->res_ctx;
int mpcc_id = 0;
if (pool && res_ctx) {
if (acquire) {
/*find pipe idx for the given stream*/
for (pipe_idx = 0; pipe_idx < pool->pipe_count; pipe_idx++) {
if (res_ctx->pipe_ctx[pipe_idx].stream == stream) {
found_pipe_idx = true;
mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst;
break;
}
}
} else
found_pipe_idx = true;/*for release pipe_idx is not required*/
if (found_pipe_idx) {
if (acquire && pool->funcs->acquire_post_bldn_3dlut)
ret = pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper);
else if (!acquire && pool->funcs->release_post_bldn_3dlut)
ret = pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shaper);
}
}
return ret;
}
static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
{
int i;
struct pipe_ctx *pipe;
for (i = 0; i < MAX_PIPES; i++) {
pipe = &context->res_ctx.pipe_ctx[i];
// Don't check flip pending on phantom pipes
if (!pipe->plane_state || (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM))
continue;
/* Must set to false to start with, due to OR in update function */
pipe->plane_state->status.is_flip_pending = false;
dc->hwss.update_pending_status(pipe);
if (pipe->plane_state->status.is_flip_pending)
return true;
}
return false;
}
/* Perform updates here which need to be deferred until next vupdate
*
* i.e. blnd lut, 3dlut, and shaper lut bypass regs are double buffered
* but forcing lut memory to shutdown state is immediate. This causes
* single frame corruption as lut gets disabled mid-frame unless shutdown
* is deferred until after entering bypass.
*/
static void process_deferred_updates(struct dc *dc)
{
int i = 0;
if (dc->debug.enable_mem_low_power.bits.cm) {
ASSERT(dc->dcn_ip->max_num_dpp);
for (i = 0; i < dc->dcn_ip->max_num_dpp; i++)
if (dc->res_pool->dpps[i]->funcs->dpp_deferred_update)
dc->res_pool->dpps[i]->funcs->dpp_deferred_update(dc->res_pool->dpps[i]);
}
}
void dc_post_update_surfaces_to_stream(struct dc *dc)
{
unsigned int i;
struct dc_state *context = dc->current_state;
if ((!dc->optimized_required) || get_seamless_boot_stream_count(context) > 0)
return;
post_surface_trace(dc);
/*
* Only relevant for DCN behavior where we can guarantee the optimization
* is safe to apply - retain the legacy behavior for DCE.
*/
if (dc->ctx->dce_version < DCE_VERSION_MAX)
TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
else {
TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
if (is_flip_pending_in_pipes(dc, context))
return;
for (i = 0; i < dc->res_pool->pipe_count; i++)
if (context->res_ctx.pipe_ctx[i].stream == NULL ||
context->res_ctx.pipe_ctx[i].plane_state == NULL) {
context->res_ctx.pipe_ctx[i].pipe_idx = (uint8_t)i;
dc->hwss.disable_plane(dc, context, &context->res_ctx.pipe_ctx[i]);
}
process_deferred_updates(dc);
dc->hwss.optimize_bandwidth(dc, context);
if (dc->hwss.update_dsc_pg)
dc->hwss.update_dsc_pg(dc, context, true);
}
dc->optimized_required = false;
}
void dc_get_default_tiling_info(const struct dc *dc, struct dc_tiling_info *tiling_info)
{
if (!dc || !tiling_info)
return;
if (dc->res_pool && dc->res_pool->funcs && dc->res_pool->funcs->get_default_tiling_info) {
dc->res_pool->funcs->get_default_tiling_info(tiling_info);
return;
}
}
bool dc_set_generic_gpio_for_stereo(bool enable,
struct gpio_service *gpio_service)
{
enum gpio_result gpio_result = GPIO_RESULT_NON_SPECIFIC_ERROR;
struct gpio_pin_info pin_info;
struct gpio *generic;
struct gpio_generic_mux_config *config = kzalloc_obj(struct gpio_generic_mux_config);
if (!config)
return false;
pin_info = dal_gpio_get_generic_pin_info(gpio_service, GPIO_ID_GENERIC, 0);
if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) {
kfree(config);
return false;
} else {
generic = dal_gpio_service_create_generic_mux(
gpio_service,
pin_info.offset,
pin_info.mask);
}
if (!generic) {
kfree(config);
return false;
}
gpio_result = dal_gpio_open(generic, GPIO_MODE_OUTPUT);
config->enable_output_from_mux = enable;
config->mux_select = GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC;
if (gpio_result == GPIO_RESULT_OK)
gpio_result = dal_mux_setup_config(generic, config);
if (gpio_result == GPIO_RESULT_OK) {
dal_gpio_close(generic);
dal_gpio_destroy_generic_mux(&generic);
kfree(config);
return true;
} else {
dal_gpio_close(generic);
dal_gpio_destroy_generic_mux(&generic);
kfree(config);
return false;
}
}
static bool is_surface_in_context(
const struct dc_state *context,
const struct dc_plane_state *plane_state)
{
int j;
for (j = 0; j < MAX_PIPES; j++) {
const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
if (plane_state == pipe_ctx->plane_state) {
return true;
}
}
return false;
}
static struct dc_update_descriptor get_plane_info_update_type(const struct dc_surface_update *u)
{
struct pipe_update_bits *update_bits = &u->surface->update_bits;
struct dc_update_descriptor update_type = { UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_NONE };
if (!u->plane_info)
return update_type;
// `plane_info` present means at least `STREAM` lock is required
elevate_update_type(&update_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
if (u->plane_info->color_space != u->surface->color_space) {
update_bits->color_space_change = 1;
elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM);
}
if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) {
update_bits->horizontal_mirror_change = 1;
elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM);
}
if (u->plane_info->rotation != u->surface->rotation) {
update_bits->rotation_change = 1;
elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);
}
if (u->plane_info->format != u->surface->format) {
update_bits->pixel_format_change = 1;
elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);
}
if (u->plane_info->stereo_format != u->surface->stereo_format) {
update_bits->stereo_format_change = 1;
elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);
}
if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) {
update_bits->per_pixel_alpha_change = 1;
elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM);
}
if (u->plane_info->global_alpha_value != u->surface->global_alpha_value) {
update_bits->global_alpha_change = 1;
elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM);
}
if (u->plane_info->dcc.enable != u->surface->dcc.enable
|| u->plane_info->dcc.dcc_ind_blk != u->surface->dcc.dcc_ind_blk
|| u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
/* During DCC on/off, stutter period is calculated before
* DCC has fully transitioned. This results in incorrect
* stutter period calculation. Triggering a full update will
* recalculate stutter period.
*/
update_bits->dcc_change = 1;
elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);
}
if (resource_pixel_format_to_bpp(u->plane_info->format) !=
resource_pixel_format_to_bpp(u->surface->format)) {
/* different bytes per element will require full bandwidth
* and DML calculation
*/
update_bits->bpp_change = 1;
elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);
}
if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
|| u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) {
update_bits->plane_size_change = 1;
elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM);
}
const struct dc_tiling_info *tiling = &u->plane_info->tiling_info;
if (memcmp(tiling, &u->surface->tiling_info, sizeof(*tiling)) != 0) {
update_bits->swizzle_change = 1;
if (tiling->flags.avoid_full_update_on_tiling_change) {
elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM);
} else {
update_bits->bandwidth_change = 1;
elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);
}
}
/* This should be UPDATE_TYPE_FAST if nothing has changed. */
return update_type;
}
static struct dc_update_descriptor get_scaling_info_update_type(
const struct dc_check_config *check_config,
const struct dc_surface_update *u)
{
struct pipe_update_bits *update_bits = &u->surface->update_bits;
struct dc_update_descriptor update_type = { UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_NONE };
if (!u->scaling_info)
return update_type;
// `scaling_info` present means at least `STREAM` lock is required
elevate_update_type(&update_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
if (u->scaling_info->src_rect.width != u->surface->src_rect.width
|| u->scaling_info->src_rect.height != u->surface->src_rect.height
|| u->scaling_info->dst_rect.width != u->surface->dst_rect.width
|| u->scaling_info->dst_rect.height != u->surface->dst_rect.height
|| u->scaling_info->clip_rect.width != u->surface->clip_rect.width
|| u->scaling_info->clip_rect.height != u->surface->clip_rect.height
|| u->scaling_info->scaling_quality.integer_scaling !=
u->surface->scaling_quality.integer_scaling) {
update_bits->scaling_change = 1;
elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);
if (u->scaling_info->src_rect.width > u->surface->src_rect.width
|| u->scaling_info->src_rect.height > u->surface->src_rect.height)
/* Making src rect bigger requires a bandwidth change */
update_bits->clock_change = 1;
if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
|| u->scaling_info->dst_rect.height < u->surface->dst_rect.height)
&& (u->scaling_info->dst_rect.width < u->surface->src_rect.width
|| u->scaling_info->dst_rect.height < u->surface->src_rect.height))
/* Making dst rect smaller requires a bandwidth change */
update_bits->bandwidth_change = 1;
if (u->scaling_info->src_rect.width > (int)check_config->max_optimizable_video_width &&
(u->scaling_info->clip_rect.width > u->surface->clip_rect.width ||
u->scaling_info->clip_rect.height > u->surface->clip_rect.height))
/* Changing clip size of a large surface may result in MPC slice count change */
update_bits->bandwidth_change = 1;
}
if (u->scaling_info->src_rect.x != u->surface->src_rect.x
|| u->scaling_info->src_rect.y != u->surface->src_rect.y
|| u->scaling_info->clip_rect.x != u->surface->clip_rect.x
|| u->scaling_info->clip_rect.y != u->surface->clip_rect.y
|| u->scaling_info->dst_rect.x != u->surface->dst_rect.x
|| u->scaling_info->dst_rect.y != u->surface->dst_rect.y) {
elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM);
update_bits->position_change = 1;
}
return update_type;
}
static struct dc_update_descriptor det_surface_update(
const struct dc_check_config *check_config,
struct dc_surface_update *u)
{
struct dc_update_descriptor overall_type = { UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_NONE };
struct pipe_update_bits *update_bits = &u->surface->update_bits;
if (u->surface->force_full_update) {
dc_pipe_update_bits_set_full(update_bits);
elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);
return overall_type;
}
dc_pipe_update_bits_clear(update_bits);
struct dc_update_descriptor inner_type = get_plane_info_update_type(u);
elevate_update_type(&overall_type, inner_type.update_type, inner_type.lock_descriptor);
inner_type = get_scaling_info_update_type(check_config, u);
elevate_update_type(&overall_type, inner_type.update_type, inner_type.lock_descriptor);
if (u->flip_addr) {
update_bits->addr_update = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
if (u->flip_addr->address.tmz_surface != u->surface->address.tmz_surface) {
update_bits->tmz_changed = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);
}
}
if (u->in_transfer_func) {
update_bits->in_transfer_func_change = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM);
}
if (u->input_csc_color_matrix) {
update_bits->input_csc_change = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
}
if (u->cursor_csc_color_matrix) {
update_bits->cursor_csc_color_matrix_change = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
}
if (u->coeff_reduction_factor) {
update_bits->coeff_reduction_change = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
}
if (u->gamut_remap_matrix) {
update_bits->gamut_remap_change = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
}
if ((u->cm && u->cm->flags.bits.blend_enable) ||
(u->gamma && dce_use_lut(u->plane_info ? u->plane_info->format : u->surface->format))) {
update_bits->gamma_change = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
}
if (u->cm && (u->cm->flags.bits.lut3d_enable || u->cm->flags.bits.shaper_enable)) {
update_bits->lut_3d = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
}
if (u->cm && u->cm->flags.bits.lut3d_dma_enable != u->surface->cm.flags.bits.lut3d_dma_enable &&
u->cm->flags.bits.lut3d_enable && u->surface->cm.flags.bits.lut3d_enable) {
/* Toggling 3DLUT loading between DMA and Host is illegal */
BREAK_TO_DEBUGGER();
}
if (u->cm && u->cm->flags.bits.lut3d_enable && !u->cm->flags.bits.lut3d_dma_enable) {
/* Host loading 3DLUT requires full update but only stream lock */
elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STREAM);
}
if (u->hdr_mult.value)
if (u->hdr_mult.value != u->surface->hdr_mult.value) {
// TODO: Should be fast?
update_bits->hdr_mult = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM);
}
if (u->sdr_white_level_nits)
if (u->sdr_white_level_nits != u->surface->sdr_white_level_nits) {
// TODO: Should be fast?
update_bits->sdr_white_level_nits = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);
}
if (u->cm_hist_control) {
update_bits->cm_hist_change = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
}
if (u->cm) {
const union dc_plane_cm_flags blend_only_flags = {
.bits = {
.blend_enable = 1,
}
};
if (u->cm->flags.bits.shaper_enable != u->surface->cm.flags.bits.shaper_enable
|| u->cm->flags.bits.blend_enable != u->surface->cm.flags.bits.blend_enable
|| u->cm->flags.bits.lut3d_enable != u->surface->cm.flags.bits.lut3d_enable
|| u->cm->flags.bits.lut3d_dma_enable != u->surface->cm.flags.bits.lut3d_dma_enable) {
update_bits->mcm_transfer_function_enable_change = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);
}
if ((u->cm->flags.all != blend_only_flags.all && u->cm->flags.all != 0) ||
(u->surface->cm.flags.all != blend_only_flags.all && u->surface->cm.flags.all != 0)) {
elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);
}
}
if (update_bits->lut_3d &&
!u->surface->cm.flags.bits.lut3d_dma_enable) {
elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);
}
if (check_config->enable_legacy_fast_update &&
(update_bits->gamma_change ||
update_bits->gamut_remap_change ||
update_bits->input_csc_change ||
update_bits->cm_hist_change ||
update_bits->coeff_reduction_change)) {
elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);
}
return overall_type;
}
/* May need to flip the desktop plane in cases where MPO plane receives a flip but desktop plane doesn't
* while both planes are flip_immediate
*/
static void force_immediate_gsl_plane_flip(struct dc *dc, struct dc_surface_update *updates, int surface_count)
{
(void)dc;
bool has_flip_immediate_plane = false;
int i;
for (i = 0; i < surface_count; i++) {
if (updates[i].surface->flip_immediate) {
has_flip_immediate_plane = true;
break;
}
}
if (has_flip_immediate_plane && surface_count > 1) {
for (i = 0; i < surface_count; i++) {
if (updates[i].surface->flip_immediate)
updates[i].surface->update_bits.addr_update = 1;
}
}
}
static struct dc_update_descriptor check_update_surfaces_for_stream(
const struct dc_check_config *check_config,
struct dc_surface_update *updates,
int surface_count,
struct dc_stream_update *stream_update)
{
struct dc_update_descriptor overall_type = { UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_NONE };
/* When countdown finishes, promote this flip to full to trigger deferred final transition */
if (check_config->deferred_transition_state && !check_config->transition_countdown_to_steady_state) {
elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);
}
if (stream_update && stream_update->pending_test_pattern) {
elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);
}
if (stream_update && stream_update->hw_cursor_req) {
elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);
}
/* some stream updates require passive update */
if (stream_update) {
elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
union stream_update_flags *su_flags = &stream_update->stream->update_flags;
if ((stream_update->src.height != 0 && stream_update->src.width != 0) ||
(stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
stream_update->integer_scaling_update)
su_flags->bits.scaling = 1;
if (check_config->enable_legacy_fast_update && stream_update->out_transfer_func)
su_flags->bits.out_tf = 1;
if (stream_update->abm_level)
su_flags->bits.abm_level = 1;
if (stream_update->dpms_off) {
su_flags->bits.dpms_off = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL | LOCK_DESCRIPTOR_LINK);
}
if (check_config->enable_legacy_fast_update && stream_update->gamut_remap)
su_flags->bits.gamut_remap = 1;
if (stream_update->wb_update)
su_flags->bits.wb_update = 1;
if (stream_update->dsc_config)
su_flags->bits.dsc_changed = 1;
if (stream_update->mst_bw_update)
su_flags->bits.mst_bw = 1;
if (stream_update->stream->freesync_on_desktop &&
(stream_update->vrr_infopacket || stream_update->allow_freesync ||
stream_update->vrr_active_variable || stream_update->vrr_active_fixed))
su_flags->bits.fams_changed = 1;
if (stream_update->scaler_sharpener_update)
su_flags->bits.scaler_sharpener = 1;
if (stream_update->sharpening_required)
su_flags->bits.sharpening_required = 1;
if (stream_update->output_color_space)
su_flags->bits.out_csc = 1;
// TODO: Make each elevation explicit, as to not override fast stream in crct_timing_adjust
if (su_flags->raw)
elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);
// Non-global cases
if (stream_update->gamut_remap) {
su_flags->bits.gamut_remap = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
}
if ((stream_update->hdr_static_metadata && !stream_update->stream->use_dynamic_meta) ||
stream_update->vrr_infopacket ||
stream_update->vsc_infopacket ||
stream_update->vsp_infopacket ||
stream_update->hfvsif_infopacket ||
stream_update->adaptive_sync_infopacket ||
stream_update->vtem_infopacket ||
stream_update->avi_infopacket) {
su_flags->bits.info_frame = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
}
if (stream_update->hdr_static_metadata && stream_update->stream->use_dynamic_meta) {
su_flags->bits.dmdata = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
}
if (stream_update->output_csc_transform) {
su_flags->bits.out_csc = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
}
if (!check_config->enable_legacy_fast_update && stream_update->out_transfer_func) {
su_flags->bits.out_tf = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
}
if (stream_update->periodic_interrupt) {
su_flags->bits.periodic_interrupt = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
}
if (stream_update->dither_option) {
su_flags->bits.dither = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
}
if (stream_update->cursor_attributes) {
su_flags->bits.cursor_attr = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
}
if (stream_update->cursor_position) {
su_flags->bits.cursor_pos = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
}
}
for (int i = 0 ; i < surface_count; i++) {
struct dc_update_descriptor inner_type =
det_surface_update(check_config, &updates[i]);
elevate_update_type(&overall_type, inner_type.update_type, inner_type.lock_descriptor);
}
return overall_type;
}
/**
* dc_check_state_update - Classify a dc_state_update by locking / re-entrancy requirements.
* @check_config: ASIC capabilities and display configuration context
* @updates: root update object describing the full desired commit
*
* Determines whether the update requires a fast, medium, or full lock
* by inspecting the stream, stream_update, and surface_updates carried on
* the root object. A probe update elevates the result to at least MED with
* the PROBE lock, so a probe-carrying commit takes the probe mutex.
*
* Return: dc_update_descriptor with update_type and lock_descriptor.
*/
struct dc_update_descriptor dc_check_state_update(
const struct dc_check_config *check_config,
const struct dc_state_update *updates)
{
struct dc_update_descriptor desc = {0};
if (updates->stream_update)
stream_update_flags_clear(&updates->stream_update->stream->update_flags);
for (int i = 0; i < updates->surface_count; i++)
dc_pipe_update_bits_clear(&updates->surface_updates[i].surface->update_bits);
desc = check_update_surfaces_for_stream(check_config, updates->surface_updates,
updates->surface_count, updates->stream_update);
if (updates->probe_updates && updates->probe_updates->probe_count > 0)
elevate_update_type(&desc, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_PROBE);
return desc;
}
/**
* dc_check_update_surfaces_for_stream - Shim for dc_check_state_update.
* @check_config: ASIC capabilities and display configuration context
* @updates: array of surface update descriptors
* @surface_count: number of entries in @updates
* @stream_update: optional stream update
*
* Packs the individual arguments into a dc_state_update and forwards to
* dc_check_state_update(). Preserved for out-of-tree and incremental callers.
*
* Return: dc_update_descriptor with update_type and lock_descriptor.
*/
struct dc_update_descriptor dc_check_update_surfaces_for_stream(
const struct dc_check_config *check_config,
struct dc_surface_update *updates,
int surface_count,
struct dc_stream_update *stream_update)
{
struct dc_state_update root = {
.stream = stream_update ? stream_update->stream : NULL,
.stream_update = stream_update,
.surface_updates = updates,
.surface_count = surface_count,
.probe_updates = NULL
};
return dc_check_state_update(check_config, &root);
}
static struct dc_stream_status *stream_get_status(
struct dc_state *ctx,
struct dc_stream_state *stream)
{
uint8_t i;
for (i = 0; i < ctx->stream_count; i++) {
if (stream == ctx->streams[i]) {
return &ctx->stream_status[i];
}
}
return NULL;
}
static const enum dc_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
static void copy_surface_update_to_plane(
struct dc_plane_state *surface,
struct dc_surface_update *srf_update)
{
if (srf_update->flip_addr) {
surface->address = srf_update->flip_addr->address;
surface->flip_immediate =
srf_update->flip_addr->flip_immediate;
surface->time.time_elapsed_in_us[surface->time.index] =
(unsigned int)(srf_update->flip_addr->flip_timestamp_in_us -
surface->time.prev_update_time_in_us);
surface->time.prev_update_time_in_us =
(unsigned int)srf_update->flip_addr->flip_timestamp_in_us;
surface->time.index++;
if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
surface->time.index = 0;
surface->triplebuffer_flips = srf_update->flip_addr->triplebuffer_flips;
}
if (srf_update->scaling_info) {
surface->scaling_quality =
srf_update->scaling_info->scaling_quality;
surface->dst_rect =
srf_update->scaling_info->dst_rect;
surface->src_rect =
srf_update->scaling_info->src_rect;
surface->clip_rect =
srf_update->scaling_info->clip_rect;
}
if (srf_update->plane_info) {
surface->color_space =
srf_update->plane_info->color_space;
surface->format =
srf_update->plane_info->format;
surface->plane_size =
srf_update->plane_info->plane_size;
surface->rotation =
srf_update->plane_info->rotation;
surface->horizontal_mirror =
srf_update->plane_info->horizontal_mirror;
surface->stereo_format =
srf_update->plane_info->stereo_format;
surface->tiling_info =
srf_update->plane_info->tiling_info;
surface->visible =
srf_update->plane_info->visible;
surface->per_pixel_alpha =
srf_update->plane_info->per_pixel_alpha;
surface->global_alpha =
srf_update->plane_info->global_alpha;
surface->global_alpha_value =
srf_update->plane_info->global_alpha_value;
surface->dcc =
srf_update->plane_info->dcc;
surface->layer_index =
srf_update->plane_info->layer_index;
}
if (srf_update->gamma) {
memcpy(&surface->gamma_correction.entries,
&srf_update->gamma->entries,
sizeof(struct dc_gamma_entries));
surface->gamma_correction.is_identity =
srf_update->gamma->is_identity;
surface->gamma_correction.num_entries =
srf_update->gamma->num_entries;
surface->gamma_correction.type =
srf_update->gamma->type;
}
if (srf_update->cm_hist_control) {
memcpy(&surface->cm_hist_control,
srf_update->cm_hist_control,
sizeof(surface->cm_hist_control));
}
if (srf_update->in_transfer_func) {
surface->in_transfer_func.sdr_ref_white_level =
srf_update->in_transfer_func->sdr_ref_white_level;
surface->in_transfer_func.tf =
srf_update->in_transfer_func->tf;
surface->in_transfer_func.type =
srf_update->in_transfer_func->type;
memcpy(&surface->in_transfer_func.tf_pts,
&srf_update->in_transfer_func->tf_pts,
sizeof(struct dc_transfer_func_distributed_points));
}
/* Shaper, 3DLUT, 1DLUT */
if (srf_update->cm) {
struct kref refcount = surface->cm.refcount;
memcpy(&surface->cm, srf_update->cm, sizeof(surface->cm));
surface->cm.refcount = refcount;
#ifndef TRIM_CM2
/* Populate mcm_luts from cm for legacy consumers (dml2, hwseq) */
surface->mcm_luts.lut1d_func = &surface->cm.blend_func;
surface->mcm_luts.shaper = &surface->cm.shaper_func;
if (srf_update->cm->flags.bits.lut3d_dma_enable) {
surface->mcm_luts.lut3d_data.lut3d_src = DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM;
surface->mcm_luts.lut3d_data.gpu_mem_params.addr = surface->cm.lut3d_dma.addr;
surface->mcm_luts.lut3d_data.gpu_mem_params.layout =
(surface->cm.lut3d_dma.swizzle == CM_LUT_3D_SWIZZLE_LINEAR_RGB) ?
DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB :
(surface->cm.lut3d_dma.swizzle == CM_LUT_3D_SWIZZLE_LINEAR_BGR) ?
DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR :
DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR;
surface->mcm_luts.lut3d_data.gpu_mem_params.format_params.format =
(surface->cm.lut3d_dma.format == CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12MSB) ?
DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12MSB :
(surface->cm.lut3d_dma.format == CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12LSB) ?
DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12LSB :
DC_CM2_GPU_MEM_FORMAT_16161616_FLOAT_FP1_5_10;
surface->mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.bias =
surface->cm.lut3d_dma.bias;
surface->mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.scale =
surface->cm.lut3d_dma.scale;
surface->mcm_luts.lut3d_data.gpu_mem_params.component_order =
DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_RGBA;
surface->mcm_luts.lut3d_data.gpu_mem_params.size = DC_CM2_GPU_MEM_SIZE_TRANSFORMED;
surface->mcm_luts.lut3d_data.mpc_3dlut_enable = (srf_update->cm->flags.bits.lut3d_enable != 0);
} else {
surface->mcm_luts.lut3d_data.lut3d_src = DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM;
surface->mcm_luts.lut3d_data.lut3d_func = &surface->cm.lut3d_func;
}
if (srf_update->cm->flags.bits.shaper_enable &&
srf_update->cm->flags.bits.lut3d_enable)
surface->mcm_shaper_3dlut_setting = DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT;
else if (srf_update->cm->flags.bits.shaper_enable)
surface->mcm_shaper_3dlut_setting = DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER;
else
surface->mcm_shaper_3dlut_setting = DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL;
#endif /* TRIM_CM2 */
}
if (srf_update->hdr_mult.value)
surface->hdr_mult =
srf_update->hdr_mult;
if (srf_update->sdr_white_level_nits)
surface->sdr_white_level_nits =
srf_update->sdr_white_level_nits;
if (srf_update->cm &&
(srf_update->cm->flags.bits.blend_enable ||
srf_update->cm->flags.bits.shaper_enable ||
srf_update->cm->flags.bits.lut3d_enable))
surface->lut_bank_a = !surface->lut_bank_a;
if (srf_update->input_csc_color_matrix)
surface->input_csc_color_matrix =
*srf_update->input_csc_color_matrix;
if (srf_update->coeff_reduction_factor)
surface->coeff_reduction_factor =
*srf_update->coeff_reduction_factor;
if (srf_update->gamut_remap_matrix)
surface->gamut_remap_matrix =
*srf_update->gamut_remap_matrix;
if (srf_update->cursor_csc_color_matrix)
surface->cursor_csc_color_matrix =
*srf_update->cursor_csc_color_matrix;
if (srf_update->bias_and_scale.bias_and_scale_valid)
surface->bias_and_scale =
srf_update->bias_and_scale;
}
static void copy_stream_update_to_stream(struct dc *dc,
struct dc_state *context,
struct dc_stream_state *stream,
struct dc_stream_update *update)
{
(void)context;
struct dc_context *dc_ctx = dc->ctx;
if (update == NULL || stream == NULL)
return;
if (update->src.height && update->src.width)
stream->src = update->src;
if (update->dst.height && update->dst.width)
stream->dst = update->dst;
if (update->out_transfer_func) {
stream->out_transfer_func.sdr_ref_white_level =
update->out_transfer_func->sdr_ref_white_level;
stream->out_transfer_func.tf = update->out_transfer_func->tf;
stream->out_transfer_func.type =
update->out_transfer_func->type;
memcpy(&stream->out_transfer_func.tf_pts,
&update->out_transfer_func->tf_pts,
sizeof(struct dc_transfer_func_distributed_points));
}
if (update->hdr_static_metadata)
stream->hdr_static_metadata = *update->hdr_static_metadata;
if (update->abm_level)
stream->abm_level = *update->abm_level;
if (update->periodic_interrupt)
stream->periodic_interrupt = *update->periodic_interrupt;
if (update->gamut_remap)
stream->gamut_remap_matrix = *update->gamut_remap;
/* Note: this being updated after mode set is currently not a use case
* however if it arises OCSC would need to be reprogrammed at the
* minimum
*/
if (update->output_color_space)
stream->output_color_space = *update->output_color_space;
if (update->output_csc_transform)
stream->csc_color_matrix = *update->output_csc_transform;
if (update->vrr_infopacket)
stream->vrr_infopacket = *update->vrr_infopacket;
if (update->hw_cursor_req)
stream->hw_cursor_req = *update->hw_cursor_req;
if (update->allow_freesync)
stream->allow_freesync = *update->allow_freesync;
if (update->vrr_active_variable)
stream->vrr_active_variable = *update->vrr_active_variable;
if (update->vrr_active_fixed)
stream->vrr_active_fixed = *update->vrr_active_fixed;
if (update->crtc_timing_adjust) {
if (stream->adjust.v_total_min != update->crtc_timing_adjust->v_total_min ||
stream->adjust.v_total_max != update->crtc_timing_adjust->v_total_max ||
stream->adjust.timing_adjust_pending)
update->crtc_timing_adjust->timing_adjust_pending = true;
stream->adjust = *update->crtc_timing_adjust;
update->crtc_timing_adjust->timing_adjust_pending = false;
}
if (update->dpms_off)
stream->dpms_off = *update->dpms_off;
if (update->hfvsif_infopacket)
stream->hfvsif_infopacket = *update->hfvsif_infopacket;
if (update->vtem_infopacket)
stream->vtem_infopacket = *update->vtem_infopacket;
if (update->vsc_infopacket)
stream->vsc_infopacket = *update->vsc_infopacket;
if (update->vsp_infopacket)
stream->vsp_infopacket = *update->vsp_infopacket;
if (update->adaptive_sync_infopacket)
stream->adaptive_sync_infopacket = *update->adaptive_sync_infopacket;
if (update->avi_infopacket)
stream->avi_infopacket = *update->avi_infopacket;
if (update->dither_option)
stream->dither_option = *update->dither_option;
if (update->pending_test_pattern)
stream->test_pattern = *update->pending_test_pattern;
/* update current stream with writeback info */
if (update->wb_update) {
unsigned int i;
stream->num_wb_info = update->wb_update->num_wb_info;
ASSERT(stream->num_wb_info <= MAX_DWB_PIPES);
for (i = 0; i < stream->num_wb_info; i++)
stream->writeback_info[i] =
update->wb_update->writeback_info[i];
}
if (update->dsc_config) {
struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg;
uint32_t old_dsc_enabled = stream->timing.flags.DSC;
uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 &&
update->dsc_config->num_slices_v != 0);
/* Use temporarry context for validating new DSC config */
struct dc_state *dsc_validate_context = dc_state_create_copy(dc->current_state);
if (dsc_validate_context) {
stream->timing.dsc_cfg = *update->dsc_config;
stream->timing.flags.DSC = enable_dsc;
if (dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context,
DC_VALIDATE_MODE_ONLY) != DC_OK) {
stream->timing.dsc_cfg = old_dsc_cfg;
stream->timing.flags.DSC = old_dsc_enabled;
update->dsc_config = NULL;
}
dc_state_release(dsc_validate_context);
} else {
DC_ERROR("Failed to allocate new validate context for DSC change\n");
update->dsc_config = NULL;
}
}
if (update->scaler_sharpener_update)
stream->scaler_sharpener_update = *update->scaler_sharpener_update;
if (update->sharpening_required)
stream->sharpening_required = *update->sharpening_required;
if (update->drr_trigger_mode) {
stream->drr_trigger_mode = *update->drr_trigger_mode;
}
}
static void backup_planes_and_stream_state(
struct dc_scratch_space *scratch,
struct dc_stream_state *stream)
{
int i;
struct dc_stream_status *status = dc_stream_get_status(stream);
if (!status)
return;
for (i = 0; i < status->plane_count; i++) {
dc_plane_copy_config(&scratch->plane_states[i], status->plane_states[i]);
}
scratch->stream_state = *stream;
}
static void restore_planes_and_stream_state(
struct dc_scratch_space *scratch,
struct dc_stream_state *stream)
{
int i;
struct dc_stream_status *status = dc_stream_get_status(stream);
if (!status)
return;
for (i = 0; i < status->plane_count; i++) {
dc_plane_copy_config(status->plane_states[i], &scratch->plane_states[i]);
}
// refcount is persistent
struct kref temp_refcount = stream->refcount;
*stream = scratch->stream_state;
stream->refcount = temp_refcount;
}
/**
* update_seamless_boot_flags() - Helper function for updating seamless boot flags
*
* @dc: Current DC state
* @context: New DC state to be programmed
* @surface_count: Number of surfaces that have an updated
* @stream: Corresponding stream to be updated in the current flip
*
* Updating seamless boot flags do not need to be part of the commit sequence. This
* helper function will update the seamless boot flags on each flip (if required)
* outside of the HW commit sequence (fast or slow).
*
* Return: void
*/
static void update_seamless_boot_flags(struct dc *dc,
struct dc_state *context,
int surface_count,
struct dc_stream_state *stream)
{
if (get_seamless_boot_stream_count(context) > 0 && (surface_count > 0 || stream->dpms_off)) {
/* Optimize seamless boot flag keeps clocks and watermarks high until
* first flip. After first flip, optimization is required to lower
* bandwidth. Important to note that it is expected UEFI will
* only light up a single display on POST, therefore we only expect
* one stream with seamless boot flag set.
*/
if (stream->apply_seamless_boot_optimization) {
stream->apply_seamless_boot_optimization = false;
if (get_seamless_boot_stream_count(context) == 0)
dc->optimized_required = true;
}
}
}
static bool full_update_required_weak(
const struct dc *dc,
const struct dc_surface_update *srf_updates,
int surface_count,
const struct dc_stream_update *stream_update,
const struct dc_stream_state *stream);
static void backup_and_set_minimal_pipe_split_policy(struct dc *dc,
struct dc_state *context,
struct pipe_split_policy_backup *policy)
{
int i;
if (!dc->config.is_vmin_only_asic) {
policy->mpc_policy = dc->debug.pipe_split_policy;
dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
}
policy->dynamic_odm_policy = dc->debug.enable_single_display_2to1_odm_policy;
dc->debug.enable_single_display_2to1_odm_policy = false;
policy->subvp_policy = dc->debug.force_disable_subvp;
dc->debug.force_disable_subvp = true;
for (i = 0; i < context->stream_count; i++) {
policy->force_odm[i] = context->streams[i]->debug.force_odm_combine_segments;
if (context->streams[i]->debug.allow_transition_for_forced_odm)
context->streams[i]->debug.force_odm_combine_segments = 0;
}
}
static void restore_minimal_pipe_split_policy(struct dc *dc,
struct dc_state *context,
struct pipe_split_policy_backup *policy)
{
uint8_t i;
if (!dc->config.is_vmin_only_asic)
dc->debug.pipe_split_policy = policy->mpc_policy;
dc->debug.enable_single_display_2to1_odm_policy =
policy->dynamic_odm_policy;
dc->debug.force_disable_subvp = policy->subvp_policy;
for (i = 0; i < context->stream_count; i++)
context->streams[i]->debug.force_odm_combine_segments = policy->force_odm[i];
}
/**
* update_planes_and_stream_state() - The function takes planes and stream
* updates as inputs and determines the appropriate update type. If update type
* is FULL, the function allocates a new context, populates and validates it.
* Otherwise, it updates current dc context. The function will return both
* new_context and new_update_type back to the caller. The function also backs
* up both current and new contexts into corresponding dc state scratch memory.
* TODO: The function does too many things, and even conditionally allocates dc
* context memory implicitly. We should consider to break it down.
*
* @dc: Current DC state
* @srf_updates: an array of surface updates
* @surface_count: surface update count
* @stream: Corresponding stream to be updated
* @stream_update: stream update
* @update_descriptor: describes what plane and stream changes to apply
* @new_update_type: [out] determined update type by the function
* @new_context: [out] new context allocated and validated if update type is
* FULL, reference to current context if update type is less than FULL.
*
* Return: true if a valid update is populated into new_context, false
* otherwise.
*/
static bool update_planes_and_stream_state(struct dc *dc,
struct dc_surface_update *srf_updates, int surface_count,
struct dc_stream_state *stream,
struct dc_stream_update *stream_update,
enum dc_update_type *new_update_type,
struct dc_state **new_context)
{
struct dc_state *context;
int i;
unsigned int j;
enum dc_update_type update_type;
const struct dc_stream_status *stream_status;
struct dc_context *dc_ctx = dc->ctx;
stream_status = dc_stream_get_status(stream);
if (!stream_status) {
if (surface_count) /* Only an error condition if surf_count non-zero*/
ASSERT(false);
return false; /* Cannot commit surface to stream that is not committed */
}
context = dc->current_state;
update_type = dc_check_update_surfaces_for_stream(
&dc->check_config, srf_updates, surface_count, stream_update).update_type;
if (full_update_required_weak(dc, srf_updates, surface_count, stream_update, stream))
update_type = UPDATE_TYPE_FULL;
/* It is possible to receive a flip for one plane while there are multiple flip_immediate planes in the same stream.
* E.g. Desktop and MPO plane are flip_immediate but only the MPO plane received a flip
* Force the other flip_immediate planes to flip so GSL doesn't wait for a flip that won't come.
*/
force_immediate_gsl_plane_flip(dc, srf_updates, surface_count);
if (update_type == UPDATE_TYPE_FULL)
backup_planes_and_stream_state(&dc->scratch.current_state, stream);
/* update current stream with the new updates */
copy_stream_update_to_stream(dc, context, stream, stream_update);
/* do not perform surface update if surface has invalid dimensions
* (all zero) and no scaling_info is provided
*/
if (surface_count > 0) {
for (i = 0; i < surface_count; i++) {
if ((srf_updates[i].surface->src_rect.width == 0 ||
srf_updates[i].surface->src_rect.height == 0 ||
srf_updates[i].surface->dst_rect.width == 0 ||
srf_updates[i].surface->dst_rect.height == 0) &&
(!srf_updates[i].scaling_info ||
srf_updates[i].scaling_info->src_rect.width == 0 ||
srf_updates[i].scaling_info->src_rect.height == 0 ||
srf_updates[i].scaling_info->dst_rect.width == 0 ||
srf_updates[i].scaling_info->dst_rect.height == 0)) {
DC_ERROR("Invalid src/dst rects in surface update!\n");
return false;
}
}
}
if (update_type == UPDATE_TYPE_FULL) {
if (stream_update) {
uint32_t dsc_changed = stream_update->stream->update_flags.bits.dsc_changed;
stream_update_flags_set_full(&stream_update->stream->update_flags);
stream_update->stream->update_flags.bits.dsc_changed = dsc_changed;
}
for (i = 0; i < surface_count; i++)
dc_pipe_update_bits_set_full(&srf_updates[i].surface->update_bits);
}
if (update_type >= update_surface_trace_level)
update_surface_trace(dc, srf_updates, surface_count);
for (i = 0; i < surface_count; i++)
copy_surface_update_to_plane(srf_updates[i].surface, &srf_updates[i]);
if (update_type >= UPDATE_TYPE_FULL) {
struct dc_plane_state *new_planes[MAX_SURFACES] = {0};
for (i = 0; i < surface_count; i++)
new_planes[i] = srf_updates[i].surface;
/* initialize scratch memory for building context */
context = dc_state_create_copy(dc->current_state);
if (context == NULL) {
DC_ERROR("Failed to allocate new validate context!\n");
return false;
}
/* For each full update, remove all existing phantom pipes first.
* Ensures that we have enough pipes for newly added MPO planes
*/
dc_state_remove_phantom_streams_and_planes(dc, context);
dc_state_release_phantom_streams_and_planes(dc, context);
/*remove old surfaces from context */
if (!dc_state_rem_all_planes_for_stream(dc, stream, context)) {
BREAK_TO_DEBUGGER();
goto fail;
}
/* add surface to context */
if (!dc_state_add_all_planes_for_stream(dc, stream, new_planes, surface_count, context)) {
BREAK_TO_DEBUGGER();
goto fail;
}
}
/* save update parameters into surface */
for (i = 0; i < surface_count; i++) {
struct dc_plane_state *surface = srf_updates[i].surface;
if (update_type != UPDATE_TYPE_MED)
continue;
if (surface->update_bits.position_change) {
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
if (pipe_ctx->plane_state != surface)
continue;
resource_build_scaling_params(pipe_ctx);
}
}
}
if (update_type == UPDATE_TYPE_FULL) {
struct pipe_split_policy_backup policy;
bool minimize = false;
if (dc->check_config.deferred_transition_state) {
if (dc->check_config.transition_countdown_to_steady_state) {
/* During countdown, all new contexts created as minimal transition states */
minimize = true;
} else {
dc->check_config.deferred_transition_state = false;
}
}
if (minimize)
backup_and_set_minimal_pipe_split_policy(dc, context, &policy);
if (dc->res_pool->funcs->validate_bandwidth(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING) != DC_OK) {
if (minimize)
restore_minimal_pipe_split_policy(dc, context, &policy);
BREAK_TO_DEBUGGER();
goto fail;
}
if (minimize)
restore_minimal_pipe_split_policy(dc, context, &policy);
}
update_seamless_boot_flags(dc, context, surface_count, stream);
*new_context = context;
*new_update_type = update_type;
if (update_type == UPDATE_TYPE_FULL)
backup_planes_and_stream_state(&dc->scratch.new_state, stream);
return true;
fail:
dc_state_release(context);
return false;
}
static void program_cursor_attributes_sequence(
struct dc *dc,
struct dc_stream_state *stream,
struct dc_state *context,
struct block_sequence_state *seq_state)
{
int k;
struct pipe_ctx *pipe_to_program = NULL;
bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc);
for (k = 0; k < (int)dc->res_pool->pipe_count; k++) {
struct pipe_ctx *tmp_pipe = &context->res_ctx.pipe_ctx[k];
if (tmp_pipe->stream != stream)
continue;
if (!pipe_to_program) {
pipe_to_program = tmp_pipe;
if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) {
hwss_add_begin_cursor_offload_update(seq_state, dc, tmp_pipe);
} else {
hwss_add_cursor_lock(seq_state, dc, pipe_to_program, true);
if (pipe_to_program->next_odm_pipe)
hwss_add_cursor_lock(seq_state, dc, pipe_to_program->next_odm_pipe, true);
}
}
hwss_add_set_cursor_attribute(seq_state, dc, tmp_pipe);
if (dc->ctx->dmub_srv)
hwss_add_send_update_cursor_info_to_dmu(seq_state, tmp_pipe, k);
if (dc->hwss.set_cursor_sdr_white_level)
hwss_add_set_cursor_sdr_white_level(seq_state, dc, tmp_pipe);
if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe)
hwss_add_update_cursor_offload_pipe(seq_state, dc, tmp_pipe);
}
if (pipe_to_program) {
if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update) {
hwss_add_commit_cursor_offload_update(seq_state, dc, pipe_to_program);
} else {
hwss_add_cursor_lock(seq_state, dc, pipe_to_program, false);
if (pipe_to_program->next_odm_pipe)
hwss_add_cursor_lock(seq_state, dc, pipe_to_program->next_odm_pipe, false);
}
}
}
static void program_cursor_position_sequence(
struct dc *dc,
struct dc_stream_state *stream,
struct dc_state *context,
struct block_sequence_state *seq_state)
{
int k;
struct pipe_ctx *pipe_to_program = NULL;
bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc);
for (k = 0; k < (int)dc->res_pool->pipe_count; k++) {
struct pipe_ctx *tmp_pipe = &context->res_ctx.pipe_ctx[k];
if (tmp_pipe->stream != stream ||
(!tmp_pipe->plane_res.mi && !tmp_pipe->plane_res.hubp) ||
!tmp_pipe->plane_state ||
(!tmp_pipe->plane_res.xfm && !tmp_pipe->plane_res.dpp) ||
(!tmp_pipe->plane_res.ipp && !tmp_pipe->plane_res.dpp))
continue;
if (!pipe_to_program) {
pipe_to_program = tmp_pipe;
if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update)
hwss_add_begin_cursor_offload_update(seq_state, dc, tmp_pipe);
else
hwss_add_cursor_lock(seq_state, dc, pipe_to_program, true);
}
hwss_add_set_cursor_position(seq_state, dc, tmp_pipe);
if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe)
hwss_add_update_cursor_offload_pipe(seq_state, dc, tmp_pipe);
if (dc->ctx->dmub_srv)
hwss_add_send_update_cursor_info_to_dmu(seq_state, tmp_pipe, k);
}
if (pipe_to_program) {
if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update)
hwss_add_commit_cursor_offload_update(seq_state, dc, pipe_to_program);
else
hwss_add_cursor_lock(seq_state, dc, pipe_to_program, false);
}
}
static void add_update_info_frame_sequence(
struct block_sequence_state *seq_state,
struct pipe_ctx *pipe_ctx)
{
bool is_hdmi_tmds;
bool is_dp;
bool is_hdmi_frl;
if (!pipe_ctx || !pipe_ctx->stream)
return;
if (pipe_ctx->stream_res.stream_enc == NULL &&
pipe_ctx->stream_res.hpo_frl_stream_enc == NULL)
return;
is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
is_hdmi_frl = dc_is_hdmi_frl_signal(pipe_ctx->stream->signal);
if (!is_hdmi_tmds && !is_dp && !is_hdmi_frl)
return;
if (is_hdmi_tmds) {
hwss_add_stream_enc_update_hdmi_info_packets(seq_state, pipe_ctx);
return;
}
if (is_hdmi_frl) {
hwss_add_hpo_frl_stream_enc_update_hdmi_info_packets(seq_state, pipe_ctx);
return;
}
if (is_dp) {
if (dp_is_128b_132b_signal(pipe_ctx)) {
hwss_add_hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num(seq_state, pipe_ctx);
hwss_add_hpo_dp_stream_enc_update_dp_info_packets(seq_state, pipe_ctx);
} else {
hwss_add_stream_enc_update_dp_info_packets_sdp_line_num(seq_state, pipe_ctx);
hwss_add_stream_enc_update_dp_info_packets(seq_state, pipe_ctx);
}
}
}
static void add_link_update_dsc_config_sequence(
struct block_sequence_state *seq_state,
struct pipe_ctx *pipe_ctx,
struct dsc_config *dsc_cfg,
struct dsc_optc_config *dsc_optc_cfg)
{
struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
struct dc_stream_state *stream = pipe_ctx->stream;
struct dc *dc = stream->ctx->dc;
struct dccg *dccg = dc->res_pool->dccg;
struct pipe_ctx *top_pipe = pipe_ctx;
struct pipe_ctx *odm_pipe = NULL;
int opp_cnt = 1;
bool should_use_dto_dscclk = false;
struct dsc_config dsc_pps_cfg;
uint8_t *dsc_packed_pps = stream->dsc_packed_pps;
int last_dsc_set_config_step = 0;
if (!stream->timing.flags.DSC || !dsc)
return;
while (top_pipe->prev_odm_pipe)
top_pipe = top_pipe->prev_odm_pipe;
for (odm_pipe = top_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
opp_cnt++;
memset(dsc_cfg, 0, sizeof(*dsc_cfg));
memset(dsc_optc_cfg, 0, sizeof(*dsc_optc_cfg));
dsc_cfg->pic_width = (stream->timing.h_addressable +
top_pipe->dsc_padding_params.dsc_hactive_padding +
stream->timing.h_border_left +
stream->timing.h_border_right) / opp_cnt;
dsc_cfg->pic_height = stream->timing.v_addressable +
stream->timing.v_border_top +
stream->timing.v_border_bottom;
dsc_cfg->pixel_encoding = stream->timing.pixel_encoding;
dsc_cfg->color_depth = stream->timing.display_color_depth;
dsc_cfg->is_odm = top_pipe->next_odm_pipe ? true : false;
dsc_cfg->dc_dsc_cfg = stream->timing.dsc_cfg;
ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h % opp_cnt == 0);
dsc_cfg->dc_dsc_cfg.num_slices_h /= opp_cnt;
dsc_cfg->dsc_padding = 0;
if (dccg && dccg->funcs->set_dto_dscclk &&
stream->timing.pix_clk_100hz > 480000)
should_use_dto_dscclk = true;
if (should_use_dto_dscclk)
hwss_add_dccg_set_dto_dscclk(seq_state, dccg, dsc->inst,
dsc_cfg->dc_dsc_cfg.num_slices_h);
last_dsc_set_config_step = *seq_state->num_steps;
hwss_add_dsc_set_config(seq_state, dsc, dsc_cfg, dsc_optc_cfg);
hwss_add_dsc_enable_with_opp(seq_state, top_pipe);
for (odm_pipe = top_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;
if (should_use_dto_dscclk)
hwss_add_dccg_set_dto_dscclk(seq_state, dccg, odm_dsc->inst,
dsc_cfg->dc_dsc_cfg.num_slices_h);
last_dsc_set_config_step = *seq_state->num_steps;
hwss_add_dsc_set_config(seq_state, odm_dsc, dsc_cfg, dsc_optc_cfg);
hwss_add_dsc_enable_with_opp(seq_state, odm_pipe);
}
if (dc_is_dp_signal(stream->signal) && !dp_is_128b_132b_signal(pipe_ctx))
hwss_add_stream_enc_dp_set_dsc_config(seq_state,
pipe_ctx->stream_res.stream_enc,
&seq_state->steps[last_dsc_set_config_step].params.dsc_set_config_simple_params.dsc_optc_cfg);
hwss_add_tg_set_dsc_config(seq_state, top_pipe->stream_res.tg,
&seq_state->steps[last_dsc_set_config_step].params.dsc_set_config_simple_params.dsc_optc_cfg, true);
memset(&dsc_pps_cfg, 0, sizeof(dsc_pps_cfg));
dsc_pps_cfg.pic_width = stream->timing.h_addressable +
stream->timing.h_border_left + stream->timing.h_border_right;
dsc_pps_cfg.pic_height = stream->timing.v_addressable +
stream->timing.v_border_top + stream->timing.v_border_bottom;
dsc_pps_cfg.pixel_encoding = stream->timing.pixel_encoding;
dsc_pps_cfg.color_depth = stream->timing.display_color_depth;
dsc_pps_cfg.is_odm = top_pipe->next_odm_pipe ? true : false;
dsc_pps_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
dsc_pps_cfg.dsc_padding = top_pipe->dsc_padding_params.dsc_hactive_padding;
if (dsc->funcs->dsc_get_packed_pps) {
dsc->funcs->dsc_get_packed_pps(dsc, &dsc_pps_cfg, dsc_packed_pps);
if (dc_is_dp_signal(stream->signal)) {
if (dp_is_128b_132b_signal(pipe_ctx))
hwss_add_hpo_dp_stream_enc_dp_set_dsc_pps_info_packet(seq_state,
pipe_ctx->stream_res.hpo_dp_stream_enc,
true, dsc_packed_pps, false);
else
hwss_add_stream_enc_dp_set_dsc_pps_info_packet(seq_state,
pipe_ctx->stream_res.stream_enc,
true, dsc_packed_pps, false);
}
else if (dc_is_hdmi_frl_signal(stream->signal)) {
hwss_add_hpo_frl_stream_enc_set_dsc_config(seq_state,
pipe_ctx->stream_res.hpo_frl_stream_enc,
&stream->timing,
dsc_packed_pps);
}
}
}
static void commit_planes_do_stream_update_sequence(struct dc *dc,
struct dc_stream_state *stream,
struct dc_stream_update *stream_update,
enum dc_update_type update_type,
struct dc_state *context,
struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],
unsigned int *num_steps)
{
int j;
struct block_sequence_state seq_state = { .steps = block_sequence, .num_steps = num_steps };
unsigned int dsc_cfg_index = 0;
*num_steps = 0; // Initialize to 0
// Stream updates
for (j = 0; j < (int)dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && pipe_ctx->stream == stream) {
if (stream_update->periodic_interrupt && dc->hwss.setup_periodic_interrupt)
hwss_add_setup_periodic_interrupt(&seq_state, dc, pipe_ctx);
if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
stream_update->vrr_infopacket ||
stream_update->vsc_infopacket ||
stream_update->vsp_infopacket ||
stream_update->hfvsif_infopacket ||
stream_update->adaptive_sync_infopacket ||
stream_update->vtem_infopacket ||
stream_update->avi_infopacket) {
resource_build_info_frame(pipe_ctx);
add_update_info_frame_sequence(&seq_state, pipe_ctx);
if (dc_is_dp_signal(pipe_ctx->stream->signal))
hwss_add_dp_trace_source_sequence(&seq_state,
pipe_ctx->stream->link,
DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
}
if (stream_update->hdr_static_metadata &&
stream->use_dynamic_meta &&
dc->hwss.set_dmdata_attributes &&
pipe_ctx->stream->dmdata_address.quad_part != 0)
hwss_add_set_dmdata_attributes(&seq_state, pipe_ctx);
if (stream_update->gamut_remap)
hwss_add_dpp_program_gamut_remap(&seq_state, pipe_ctx);
if (stream_update->output_csc_transform)
hwss_add_program_output_csc(&seq_state, dc, pipe_ctx,
stream->output_color_space,
stream->csc_color_matrix.matrix,
pipe_ctx->stream_res.opp->inst);
if (stream_update->dither_option) {
struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
resource_build_bit_depth_reduction_params(pipe_ctx->stream,
&pipe_ctx->stream->bit_depth_params);
hwss_add_opp_program_fmt(&seq_state, pipe_ctx->stream_res.opp,
&stream->bit_depth_params,
&stream->clamping);
while (odm_pipe) {
hwss_add_opp_program_fmt(&seq_state, odm_pipe->stream_res.opp,
&stream->bit_depth_params,
&stream->clamping);
odm_pipe = odm_pipe->next_odm_pipe;
}
}
if (stream_update->cursor_attributes)
program_cursor_attributes_sequence(dc, stream, context, &seq_state);
if (stream_update->cursor_position)
program_cursor_position_sequence(dc, stream, context, &seq_state);
/* Full fe update*/
if (update_type == UPDATE_TYPE_FAST)
continue;
if (stream_update->dsc_config)
if (dsc_cfg_index < MAX_PIPES) {
struct dsc_config dsc_cfg;
struct dsc_optc_config dsc_optc_cfg;
add_link_update_dsc_config_sequence(&seq_state,
pipe_ctx,
&dsc_cfg,
&dsc_optc_cfg);
}
if (stream_update->mst_bw_update) {
if (stream_update->mst_bw_update->is_increase)
hwss_add_link_increase_mst_payload(&seq_state,
pipe_ctx,
stream_update->mst_bw_update->mst_stream_bw);
else
hwss_add_link_reduce_mst_payload(&seq_state,
pipe_ctx,
stream_update->mst_bw_update->mst_stream_bw);
}
if (stream_update->pending_test_pattern) {
/*
* test pattern params depends on ODM topology
* changes that we could be applying to front
* end. Since at the current stage front end
* changes are not yet applied. We can only
* apply test pattern in hw based on current
* state and populate the final test pattern
* params in new state. If current and new test
* pattern params are different as result of
* different ODM topology being used, it will be
* detected and handle during front end
* programming update.
*/
hwss_add_dp_set_test_pattern(&seq_state,
stream->link,
stream->test_pattern.type,
stream->test_pattern.color_space,
stream->test_pattern.p_link_settings,
stream->test_pattern.p_custom_pattern,
stream->test_pattern.cust_pattern_size);
resource_build_test_pattern_params(&context->res_ctx, pipe_ctx);
}
if (stream_update->dpms_off) {
// DPMS should not use partially updated pipe context
struct pipe_ctx *dpms_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[j];
if (*stream_update->dpms_off) {
hwss_add_link_set_dpms_off(&seq_state, dpms_pipe_ctx);
/* for dpms, keep acquired resources*/
if (dpms_pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)
hwss_add_disable_audio_stream(&seq_state, dpms_pipe_ctx);
hwss_add_dc_set_optimized_required(&seq_state, dc, true);
} else {
if (get_seamless_boot_stream_count(context) == 0 && dc->hwss.prepare_bandwidth_sequence)
dc->hwss.prepare_bandwidth_sequence(dc, dc->current_state, &seq_state);
hwss_add_link_set_dpms_on(&seq_state, dc->current_state, dpms_pipe_ctx);
}
} else if (pipe_ctx->stream->link->wa_flags.blank_stream_on_ocs_change && stream_update->output_color_space
&& !stream->dpms_off && dc_is_dp_signal(pipe_ctx->stream->signal)) {
/*
* Workaround for firmware issue in some receivers where they don't pick up
* correct output color space unless DP link is disabled/re-enabled
*/
hwss_add_link_set_dpms_on(&seq_state, dc->current_state, pipe_ctx);
}
if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
bool should_program_abm = true;
// if otg funcs defined check if blanked before programming
if (pipe_ctx->stream_res.tg->funcs->is_blanked)
if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
should_program_abm = false;
if (should_program_abm) {
if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) {
hwss_add_abm_set_immediate_disable(&seq_state, dc, pipe_ctx);
} else {
hwss_add_abm_set_level(&seq_state, pipe_ctx->stream_res.abm, stream->abm_level);
}
}
}
}
}
}
static void commit_planes_do_stream_update(struct dc *dc,
struct dc_stream_state *stream,
struct dc_stream_update *stream_update,
enum dc_update_type update_type,
struct dc_state *context)
{
unsigned int j;
// Check if block sequence programming is enabled
if (dc->debug.enable_block_sequence_programming) {
unsigned int num_steps = 0;
// Build the block sequence using context's pre-allocated array
commit_planes_do_stream_update_sequence(dc, stream, stream_update,
update_type, context, context->block_sequence, &num_steps);
// Execute the block sequence
if (num_steps > 0)
hwss_execute_sequence(dc, context->block_sequence, num_steps);
return;
}
// Legacy path (existing implementation)
// Stream updates
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && pipe_ctx->stream == stream) {
if (stream_update->periodic_interrupt && dc->hwss.setup_periodic_interrupt)
dc->hwss.setup_periodic_interrupt(dc, pipe_ctx);
if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
stream_update->vrr_infopacket ||
stream_update->vsc_infopacket ||
stream_update->vsp_infopacket ||
stream_update->hfvsif_infopacket ||
stream_update->adaptive_sync_infopacket ||
stream_update->vtem_infopacket ||
stream_update->avi_infopacket) {
resource_build_info_frame(pipe_ctx);
dc->hwss.update_info_frame(pipe_ctx);
if (dc_is_dp_signal(pipe_ctx->stream->signal))
dc->link_srv->dp_trace_source_sequence(
pipe_ctx->stream->link,
DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
}
if (stream_update->hdr_static_metadata &&
stream->use_dynamic_meta &&
dc->hwss.set_dmdata_attributes &&
pipe_ctx->stream->dmdata_address.quad_part != 0)
dc->hwss.set_dmdata_attributes(pipe_ctx);
if (stream_update->gamut_remap)
dc_stream_set_gamut_remap(dc, stream);
if (stream_update->output_csc_transform)
dc_stream_program_csc_matrix(dc, stream);
if (stream_update->dither_option) {
struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
resource_build_bit_depth_reduction_params(pipe_ctx->stream,
&pipe_ctx->stream->bit_depth_params);
pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
&stream->bit_depth_params,
&stream->clamping);
while (odm_pipe) {
odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,
&stream->bit_depth_params,
&stream->clamping);
odm_pipe = odm_pipe->next_odm_pipe;
}
}
if (stream_update->cursor_attributes)
program_cursor_attributes(dc, stream);
if (stream_update->cursor_position)
program_cursor_position(dc, stream);
/* Full fe update*/
if (update_type == UPDATE_TYPE_FAST)
continue;
if (stream_update->dsc_config)
dc->link_srv->update_dsc_config(pipe_ctx);
if (stream_update->mst_bw_update) {
if (stream_update->mst_bw_update->is_increase)
dc->link_srv->increase_mst_payload(pipe_ctx,
stream_update->mst_bw_update->mst_stream_bw);
else
dc->link_srv->reduce_mst_payload(pipe_ctx,
stream_update->mst_bw_update->mst_stream_bw);
}
if (stream_update->pending_test_pattern) {
/*
* test pattern params depends on ODM topology
* changes that we could be applying to front
* end. Since at the current stage front end
* changes are not yet applied. We can only
* apply test pattern in hw based on current
* state and populate the final test pattern
* params in new state. If current and new test
* pattern params are different as result of
* different ODM topology being used, it will be
* detected and handle during front end
* programming update.
*/
dc->link_srv->dp_set_test_pattern(stream->link,
stream->test_pattern.type,
stream->test_pattern.color_space,
stream->test_pattern.p_link_settings,
stream->test_pattern.p_custom_pattern,
stream->test_pattern.cust_pattern_size);
resource_build_test_pattern_params(&context->res_ctx, pipe_ctx);
}
// DPMS should not use partially updated pipe context
struct pipe_ctx *dpms_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[j];
if (stream_update->dpms_off) {
if (*stream_update->dpms_off) {
dc->link_srv->set_dpms_off(dpms_pipe_ctx);
/* for dpms, keep acquired resources*/
if (dpms_pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only) {
struct audio *audio = dpms_pipe_ctx->stream_res.audio;
audio->funcs->az_disable(audio);
}
dc->optimized_required = true;
} else {
if (get_seamless_boot_stream_count(context) == 0)
dc->hwss.prepare_bandwidth(dc, dc->current_state);
dc->link_srv->set_dpms_on(dc->current_state, dpms_pipe_ctx);
}
} else if (dpms_pipe_ctx->stream->link->wa_flags.blank_stream_on_ocs_change &&
stream_update->output_color_space &&
!stream->dpms_off && dc_is_dp_signal(dpms_pipe_ctx->stream->signal)) {
/*
* Workaround for firmware issue in some receivers where they don't pick up
* correct output color space unless DP link is disabled/re-enabled
*/
dc->link_srv->set_dpms_on(dc->current_state, dpms_pipe_ctx);
}
if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
bool should_program_abm = true;
// if otg funcs defined check if blanked before programming
if (pipe_ctx->stream_res.tg->funcs->is_blanked)
if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
should_program_abm = false;
if (should_program_abm) {
if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) {
dc->hwss.set_abm_immediate_disable(pipe_ctx);
} else {
pipe_ctx->stream_res.abm->funcs->set_abm_level(
pipe_ctx->stream_res.abm, stream->abm_level);
}
}
}
}
}
}
static bool dc_dmub_should_send_dirty_rect_cmd(struct dc *dc, struct dc_stream_state *stream)
{
(void)dc;
if ((stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1
|| stream->link->psr_settings.psr_version == DC_PSR_VERSION_1)
&& stream->ctx->dce_version >= DCN_VERSION_3_1)
return true;
if (stream->link->replay_settings.config.replay_supported)
return true;
if (stream->ctx->dce_version >= DCN_VERSION_3_5 && stream->abm_level)
return true;
return false;
}
void dc_dmub_update_dirty_rect(struct dc *dc,
int surface_count,
struct dc_stream_state *stream,
const struct dc_surface_update *srf_updates,
struct dc_state *context)
{
union dmub_rb_cmd cmd;
struct dmub_cmd_update_dirty_rect_data *update_dirty_rect;
int i;
unsigned int j;
unsigned int panel_inst = 0;
if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream))
return;
if (!dc->config.frame_update_cmd_version2 && !dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
return;
memset(&cmd, 0x0, sizeof(cmd));
cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT;
cmd.update_dirty_rect.header.sub_type = 0;
cmd.update_dirty_rect.header.payload_bytes =
sizeof(cmd.update_dirty_rect) -
sizeof(cmd.update_dirty_rect.header);
update_dirty_rect = &cmd.update_dirty_rect.update_dirty_rect_data;
for (i = 0; i < surface_count; i++) {
struct dc_plane_state *plane_state = srf_updates[i].surface;
const struct dc_flip_addrs *flip_addr = srf_updates[i].flip_addr;
if (!srf_updates[i].surface || !flip_addr)
continue;
/* Do not send in immediate flip mode */
if (srf_updates[i].surface->flip_immediate)
continue;
if (dc->config.frame_update_cmd_version2)
update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_2;
else
update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1;
update_dirty_rect->dirty_rect_count = (uint8_t)flip_addr->dirty_rect_count;
memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects,
sizeof(flip_addr->dirty_rects));
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
if (pipe_ctx->stream != stream)
continue;
if (pipe_ctx->plane_state != plane_state)
continue;
update_dirty_rect->panel_inst = (uint8_t)panel_inst;
update_dirty_rect->pipe_idx = (uint8_t)j;
update_dirty_rect->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
}
}
}
static void build_dmub_update_dirty_rect(
struct dc *dc,
int surface_count,
struct dc_stream_state *stream,
struct dc_surface_update *srf_updates,
struct dc_state *context,
struct dc_dmub_cmd dc_dmub_cmd[],
unsigned int *dmub_cmd_count)
{
union dmub_rb_cmd cmd;
struct dmub_cmd_update_dirty_rect_data *update_dirty_rect;
int i;
unsigned int j;
unsigned int panel_inst = 0;
if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream))
return;
if (!dc->config.frame_update_cmd_version2 && !dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
return;
memset(&cmd, 0x0, sizeof(cmd));
cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT;
cmd.update_dirty_rect.header.sub_type = 0;
cmd.update_dirty_rect.header.payload_bytes =
sizeof(cmd.update_dirty_rect) -
sizeof(cmd.update_dirty_rect.header);
update_dirty_rect = &cmd.update_dirty_rect.update_dirty_rect_data;
for (i = 0; i < surface_count; i++) {
struct dc_plane_state *plane_state = srf_updates[i].surface;
const struct dc_flip_addrs *flip_addr = srf_updates[i].flip_addr;
if (!srf_updates[i].surface || !flip_addr)
continue;
/* Do not send in immediate flip mode */
if (srf_updates[i].surface->flip_immediate)
continue;
if (dc->config.frame_update_cmd_version2)
update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_2;
else
update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1;
update_dirty_rect->dirty_rect_count = (uint8_t)flip_addr->dirty_rect_count;
memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects,
sizeof(flip_addr->dirty_rects));
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
if (pipe_ctx->stream != stream)
continue;
if (pipe_ctx->plane_state != plane_state)
continue;
update_dirty_rect->panel_inst = (uint8_t)panel_inst;
update_dirty_rect->pipe_idx = (uint8_t)j;
update_dirty_rect->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
dc_dmub_cmd[*dmub_cmd_count].dmub_cmd = cmd;
dc_dmub_cmd[*dmub_cmd_count].wait_type = DM_DMUB_WAIT_TYPE_NO_WAIT;
(*dmub_cmd_count)++;
}
}
}
/**
* dc_check_address_only_update - Check if addr_update is the sole flag set
*
* @update_bits: The pipe update bits to check
*
* Determines whether an update contains only an address change with no other
* pending updates.
*
* Return: %true if addr_update is the sole bit set, %false otherwise.
*/
bool dc_check_address_only_update(struct pipe_update_bits update_bits)
{
struct pipe_update_bits check = update_bits; /* 1. Copy all flags from input */
check.addr_update = 0; /* 2. Zero the addr_update bit in the copy */
return update_bits.addr_update && /* 3. Check addr_update was set in original */
!dc_pipe_update_bits_is_any_set(&check); /* 4. Check no other bits remain in the copy */
}
/**
* build_dmub_cmd_list() - Build an array of DMCUB commands to be sent to DMCUB
*
* @dc: Current DC state
* @srf_updates: Array of surface updates
* @surface_count: Number of surfaces that have an updated
* @stream: Corresponding stream to be updated in the current flip
* @context: New DC state to be programmed
*
* @dc_dmub_cmd: Array of DMCUB commands to be sent to DMCUB
* @dmub_cmd_count: Count indicating the number of DMCUB commands in dc_dmub_cmd array
*
* This function builds an array of DMCUB commands to be sent to DMCUB. This function is required
* to build an array of commands and have them sent while the OTG lock is acquired.
*
* Return: void
*/
static void build_dmub_cmd_list(struct dc *dc,
struct dc_surface_update *srf_updates,
int surface_count,
struct dc_stream_state *stream,
struct dc_state *context,
struct dc_dmub_cmd dc_dmub_cmd[],
unsigned int *dmub_cmd_count)
{
// Initialize cmd count to 0
*dmub_cmd_count = 0;
build_dmub_update_dirty_rect(dc, surface_count, stream, srf_updates, context, dc_dmub_cmd, dmub_cmd_count);
}
static void commit_plane_for_stream_offload_fams2_flip(struct dc *dc,
struct dc_surface_update *srf_updates,
int surface_count,
struct dc_stream_state *stream,
struct dc_state *context)
{
int i;
unsigned int j;
/* update dirty rect for PSR */
dc_dmub_update_dirty_rect(dc, surface_count, stream,
srf_updates, context);
/* Perform requested Updates */
for (i = 0; i < surface_count; i++) {
struct dc_plane_state *plane_state = srf_updates[i].surface;
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
if (!should_update_pipe_for_stream(context, pipe_ctx, stream))
continue;
if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))
continue;
/* update pipe context for plane */
if (pipe_ctx->plane_state->update_bits.addr_update)
dc->hwss.update_plane_addr(dc, pipe_ctx);
}
}
/* Send commands to DMCUB */
dc_dmub_srv_fams2_passthrough_flip(dc,
context,
stream,
srf_updates,
surface_count);
}
static void commit_planes_for_stream_fast(struct dc *dc,
struct dc_surface_update *srf_updates,
int surface_count,
struct dc_stream_state *stream,
struct dc_stream_update *stream_update,
enum dc_update_type update_type,
struct dc_state *context)
{
int i;
unsigned int j;
struct pipe_ctx *top_pipe_to_program = NULL;
struct dc_stream_status *stream_status = NULL;
bool should_offload_fams2_flip = false;
bool should_lock_all_pipes = (update_type != UPDATE_TYPE_FAST);
if (should_lock_all_pipes)
determine_pipe_unlock_order(dc, context);
if (dc->debug.fams2_config.bits.enable &&
dc->debug.fams2_config.bits.enable_offload_flip &&
dc_state_is_fams2_in_use(dc, context)) {
/* if not offloading to HWFQ, offload to FAMS2 if needed */
should_offload_fams2_flip = true;
for (i = 0; i < surface_count; i++) {
if (srf_updates[i].surface &&
dc_pipe_update_bits_is_any_set(&srf_updates[i].surface->update_bits) &&
!dc_check_address_only_update(srf_updates[i].surface->update_bits)) {
/* more than address update, need to acquire FAMS2 lock */
should_offload_fams2_flip = false;
break;
}
}
if (stream_update) {
/* more than address update, need to acquire FAMS2 lock */
should_offload_fams2_flip = false;
}
}
dc_exit_ips_for_hw_access(dc);
dc_z10_restore(dc);
top_pipe_to_program = resource_get_otg_master_for_stream(
&context->res_ctx,
stream);
if (!top_pipe_to_program)
return;
for (i = 0; i < (int)dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
if (pipe->stream && pipe->plane_state) {
if (!dc->debug.using_dml2)
set_p_state_switch_method(dc, context, pipe);
if (dc->debug.visual_confirm)
dc_update_visual_confirm_color(dc, context, pipe);
}
}
for (i = 0; i < surface_count; i++) {
struct dc_plane_state *plane_state = srf_updates[i].surface;
/*set logical flag for lock/unlock use*/
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
if (!pipe_ctx->plane_state)
continue;
if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))
continue;
pipe_ctx->plane_state->triplebuffer_flips = false;
if (update_type == UPDATE_TYPE_FAST &&
dc->hwss.program_triplebuffer != NULL &&
!pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {
/*triple buffer for VUpdate only*/
pipe_ctx->plane_state->triplebuffer_flips = true;
}
}
}
stream_status = dc_state_get_stream_status(context, stream);
if (should_offload_fams2_flip) {
commit_plane_for_stream_offload_fams2_flip(dc,
srf_updates,
surface_count,
stream,
context);
} else if (stream_status) {
build_dmub_cmd_list(dc,
srf_updates,
surface_count,
stream,
context,
context->dc_dmub_cmd,
&(context->dmub_cmd_count));
hwss_build_fast_sequence(dc,
context->dc_dmub_cmd,
context->dmub_cmd_count,
context->block_sequence,
&(context->block_sequence_steps),
top_pipe_to_program,
stream_status,
context);
hwss_execute_sequence(dc,
context->block_sequence,
context->block_sequence_steps);
}
/* Clear update flags so next flip doesn't have redundant programming
* (if there's no stream update, the update flags are not cleared).
* Surface updates are cleared unconditionally at the beginning of each flip,
* so no need to clear here.
*/
if (top_pipe_to_program->stream)
stream_update_flags_clear(&top_pipe_to_program->stream->update_flags);
}
static void commit_planes_for_stream(struct dc *dc,
const struct dc_surface_update *srf_updates,
int surface_count,
struct dc_stream_state *stream,
struct dc_stream_update *stream_update,
enum dc_update_type update_type,
struct dc_state *context)
{
int i;
unsigned int j, pipe_idx;
struct pipe_ctx *top_pipe_to_program = NULL;
bool should_lock_all_pipes = (update_type != UPDATE_TYPE_FAST);
bool subvp_prev_use = false;
bool subvp_curr_use = false;
uint8_t current_stream_mask = 0;
if (should_lock_all_pipes)
determine_pipe_unlock_order(dc, context);
// Once we apply the new subvp context to hardware it won't be in the
// dc->current_state anymore, so we have to cache it before we apply
// the new SubVP context
subvp_prev_use = false;
dc_exit_ips_for_hw_access(dc);
dc_z10_restore(dc);
if (update_type == UPDATE_TYPE_FULL && dc->optimized_required)
hwss_process_outstanding_hw_updates(dc, dc->current_state);
if (update_type != UPDATE_TYPE_FAST && dc->res_pool->funcs->prepare_mcache_programming)
dc->res_pool->funcs->prepare_mcache_programming(dc, context);
for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[pipe_idx];
if (pipe->stream && pipe->plane_state) {
if (!dc->debug.using_dml2)
set_p_state_switch_method(dc, context, pipe);
if (dc->debug.visual_confirm)
dc_update_visual_confirm_color(dc, context, pipe);
}
}
if (update_type == UPDATE_TYPE_FULL) {
dc_allow_idle_optimizations(dc, false);
if (get_seamless_boot_stream_count(context) == 0)
dc->hwss.prepare_bandwidth(dc, context);
if (dc->hwss.update_dsc_pg)
dc->hwss.update_dsc_pg(dc, context, false);
context_clock_trace(dc, context);
}
if (update_type == UPDATE_TYPE_FULL)
hwss_wait_for_outstanding_hw_updates(dc, dc->current_state);
top_pipe_to_program = resource_get_otg_master_for_stream(
&context->res_ctx,
stream);
ASSERT(top_pipe_to_program != NULL);
for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {
struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_idx];
// Check old context for SubVP
subvp_prev_use |= (dc_state_get_pipe_subvp_type(dc->current_state, old_pipe) == SUBVP_PHANTOM);
if (subvp_prev_use)
break;
}
for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[pipe_idx];
if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {
subvp_curr_use = true;
break;
}
}
if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {
struct pipe_ctx *mpcc_pipe;
struct pipe_ctx *odm_pipe;
for (mpcc_pipe = top_pipe_to_program; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)
for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;
}
if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
if (top_pipe_to_program &&
top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
if (should_use_dmub_inbox1_lock(dc, stream->link)) {
union dmub_hw_lock_flags hw_locks = { 0 };
struct dmub_hw_lock_inst_flags inst_flags = { 0 };
hw_locks.bits.lock_dig = 1;
inst_flags.dig_inst = (uint8_t)top_pipe_to_program->stream_res.tg->inst;
dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
true,
&hw_locks,
&inst_flags);
} else
top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable(
top_pipe_to_program->stream_res.tg);
}
if (dc->hwss.wait_for_dcc_meta_propagation) {
dc->hwss.wait_for_dcc_meta_propagation(dc, top_pipe_to_program);
}
if (dc->hwseq->funcs.wait_for_pipe_update_if_needed)
dc->hwseq->funcs.wait_for_pipe_update_if_needed(dc, top_pipe_to_program, update_type < UPDATE_TYPE_FULL);
if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
if (dc->hwss.subvp_pipe_control_lock)
dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, NULL, subvp_prev_use);
if (dc->hwss.dmub_hw_control_lock)
dc->hwss.dmub_hw_control_lock(dc, context, true);
dc->hwss.interdependent_update_lock(dc, context, true);
} else {
if (dc->hwss.subvp_pipe_control_lock)
dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);
if (dc->hwss.dmub_hw_control_lock)
dc->hwss.dmub_hw_control_lock(dc, context, true);
/* Lock the top pipe while updating plane addrs, since freesync requires
* plane addr update event triggers to be synchronized.
* top_pipe_to_program is expected to never be NULL
*/
dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
}
dc_dmub_update_dirty_rect(dc, surface_count, stream, srf_updates, context);
// Stream updates
if (stream_update)
commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
if (surface_count == 0) {
/*
* In case of turning off screen, no need to program front end a second time.
* just return after program blank.
*/
if (dc->hwss.apply_ctx_for_surface)
dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
if (dc->hwss.program_front_end_for_ctx)
dc->hwss.program_front_end_for_ctx(dc, context);
if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
dc->hwss.interdependent_update_lock(dc, context, false);
} else {
dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
}
dc->hwss.post_unlock_program_front_end(dc, context);
if (update_type != UPDATE_TYPE_FAST)
if (dc->hwss.commit_subvp_config)
dc->hwss.commit_subvp_config(dc, context);
/* Since phantom pipe programming is moved to post_unlock_program_front_end,
* move the SubVP lock to after the phantom pipes have been setup
*/
if (dc->hwss.subvp_pipe_control_lock)
dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes,
NULL, subvp_prev_use);
if (dc->hwss.dmub_hw_control_lock)
dc->hwss.dmub_hw_control_lock(dc, context, false);
return;
}
if (update_type != UPDATE_TYPE_FAST) {
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
if ((dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP ||
dc->debug.visual_confirm == VISUAL_CONFIRM_MCLK_SWITCH) &&
pipe_ctx->stream && pipe_ctx->plane_state) {
/* Only update visual confirm for SUBVP and Mclk switching here.
* The bar appears on all pipes, so we need to update the bar on all displays,
* so the information doesn't get stale.
*/
dc->hwss.update_visual_confirm_color(dc, pipe_ctx,
pipe_ctx->plane_res.hubp->inst);
}
}
}
for (i = 0; i < surface_count; i++) {
struct dc_plane_state *plane_state = srf_updates[i].surface;
/*set logical flag for lock/unlock use*/
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
if (!pipe_ctx->plane_state)
continue;
if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))
continue;
pipe_ctx->plane_state->triplebuffer_flips = false;
if (update_type == UPDATE_TYPE_FAST &&
dc->hwss.program_triplebuffer != NULL &&
!pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {
/*triple buffer for VUpdate only*/
pipe_ctx->plane_state->triplebuffer_flips = true;
}
}
if (update_type == UPDATE_TYPE_FULL) {
/* force vsync flip when reconfiguring pipes to prevent underflow */
plane_state->flip_immediate = false;
plane_state->triplebuffer_flips = false;
}
}
// Update Type FULL, Surface updates
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
if (!pipe_ctx->top_pipe &&
!pipe_ctx->prev_odm_pipe &&
should_update_pipe_for_stream(context, pipe_ctx, stream)) {
struct dc_stream_status *pipe_stream_status = NULL;
if (!pipe_ctx->plane_state)
continue;
/* Full fe update*/
if (update_type == UPDATE_TYPE_FAST)
continue;
pipe_stream_status =
stream_get_status(context, pipe_ctx->stream);
if (dc->hwss.apply_ctx_for_surface && pipe_stream_status)
dc->hwss.apply_ctx_for_surface(
dc, pipe_ctx->stream, pipe_stream_status->plane_count, context);
}
}
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
if (!pipe_ctx->plane_state)
continue;
/* Full fe update*/
if (update_type == UPDATE_TYPE_FAST)
continue;
ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
/*turn off triple buffer for full update*/
dc->hwss.program_triplebuffer(
dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
}
}
if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
dc->hwss.program_front_end_for_ctx(dc, context);
//Pipe busy until some frame and line #
if (dc->hwseq->funcs.set_wait_for_update_needed_for_pipe && update_type == UPDATE_TYPE_FULL) {
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
dc->hwseq->funcs.set_wait_for_update_needed_for_pipe(dc, pipe_ctx);
}
}
if (dc->debug.validate_dml_output) {
for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {
struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
if (cur_pipe->stream == NULL)
continue;
cur_pipe->plane_res.hubp->funcs->validate_dml_output(
cur_pipe->plane_res.hubp, dc->ctx,
&context->res_ctx.pipe_ctx[pipe_idx].rq_regs,
&context->res_ctx.pipe_ctx[pipe_idx].dlg_regs,
&context->res_ctx.pipe_ctx[pipe_idx].ttu_regs);
}
}
}
// Update Type FAST, Surface updates
if (update_type == UPDATE_TYPE_FAST) {
if (dc->hwss.set_flip_control_gsl)
for (i = 0; i < surface_count; i++) {
struct dc_plane_state *plane_state = srf_updates[i].surface;
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
if (!should_update_pipe_for_stream(context, pipe_ctx, stream))
continue;
if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))
continue;
// GSL has to be used for flip immediate
dc->hwss.set_flip_control_gsl(pipe_ctx,
pipe_ctx->plane_state->flip_immediate);
}
}
/* Perform requested Updates */
for (i = 0; i < surface_count; i++) {
struct dc_plane_state *plane_state = srf_updates[i].surface;
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
if (!should_update_pipe_for_stream(context, pipe_ctx, stream))
continue;
if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))
continue;
if (srf_updates[i].cm &&
srf_updates[i].cm->flags.bits.lut3d_enable &&
srf_updates[i].cm->flags.bits.lut3d_dma_enable &&
dc->hwss.trigger_3dlut_dma_load)
dc->hwss.trigger_3dlut_dma_load(dc, pipe_ctx);
/*program triple buffer after lock based on flip type*/
if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
/*only enable triplebuffer for fast_update*/
dc->hwss.program_triplebuffer(
dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
}
if (pipe_ctx->plane_state->update_bits.addr_update)
dc->hwss.update_plane_addr(dc, pipe_ctx);
}
}
}
if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
dc->hwss.interdependent_update_lock(dc, context, false);
} else {
dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
}
if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
if (top_pipe_to_program &&
top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
top_pipe_to_program->stream_res.tg,
CRTC_STATE_VACTIVE);
top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
top_pipe_to_program->stream_res.tg,
CRTC_STATE_VBLANK);
top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
top_pipe_to_program->stream_res.tg,
CRTC_STATE_VACTIVE);
if (should_use_dmub_inbox1_lock(dc, stream->link)) {
union dmub_hw_lock_flags hw_locks = { 0 };
struct dmub_hw_lock_inst_flags inst_flags = { 0 };
hw_locks.bits.lock_dig = 1;
inst_flags.dig_inst = (uint8_t)top_pipe_to_program->stream_res.tg->inst;
dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
false,
&hw_locks,
&inst_flags);
} else
top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable(
top_pipe_to_program->stream_res.tg);
}
if (subvp_curr_use) {
/* If enabling subvp or transitioning from subvp->subvp, enable the
* phantom streams before we program front end for the phantom pipes.
*/
if (update_type != UPDATE_TYPE_FAST) {
if (dc->hwss.enable_phantom_streams)
dc->hwss.enable_phantom_streams(dc, context);
}
}
if (update_type != UPDATE_TYPE_FAST)
dc->hwss.post_unlock_program_front_end(dc, context);
if (subvp_prev_use && !subvp_curr_use) {
/* If disabling subvp, disable phantom streams after front end
* programming has completed (we turn on phantom OTG in order
* to complete the plane disable for phantom pipes).
*/
if (dc->hwss.disable_phantom_streams)
dc->hwss.disable_phantom_streams(dc, context);
}
if (update_type != UPDATE_TYPE_FAST)
if (dc->hwss.commit_subvp_config)
dc->hwss.commit_subvp_config(dc, context);
/* Since phantom pipe programming is moved to post_unlock_program_front_end,
* move the SubVP lock to after the phantom pipes have been setup
*/
if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
if (dc->hwss.subvp_pipe_control_lock)
dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, NULL, subvp_prev_use);
if (dc->hwss.dmub_hw_control_lock)
dc->hwss.dmub_hw_control_lock(dc, context, false);
} else {
if (dc->hwss.subvp_pipe_control_lock)
dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);
if (dc->hwss.dmub_hw_control_lock)
dc->hwss.dmub_hw_control_lock(dc, context, false);
}
// Fire manual trigger only when bottom plane is flipped
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
if (!pipe_ctx->plane_state)
continue;
if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe ||
!pipe_ctx->stream || !should_update_pipe_for_stream(context, pipe_ctx, stream) ||
!pipe_ctx->plane_state->update_bits.addr_update ||
pipe_ctx->plane_state->skip_manual_trigger)
continue;
if (dc->hwss.program_cursor_offload_now)
dc->hwss.program_cursor_offload_now(dc, pipe_ctx);
if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
}
current_stream_mask = get_stream_mask(dc, context);
if (current_stream_mask != context->stream_mask) {
context->stream_mask = current_stream_mask;
dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, current_stream_mask);
}
}
/**
* could_mpcc_tree_change_for_active_pipes - Check if an OPP associated with MPCC might change
*
* @dc: Used to get the current state status
* @stream: Target stream, which we want to remove the attached planes
* @srf_updates: Array of surface updates
* @surface_count: Number of surface update
* @is_plane_addition: [in] Fill out with true if it is a plane addition case
*
* DCN32x and newer support a feature named Dynamic ODM which can conflict with
* the MPO if used simultaneously in some specific configurations (e.g.,
* 4k@144). This function checks if the incoming context requires applying a
* transition state with unnecessary pipe splitting and ODM disabled to
* circumvent our hardware limitations to prevent this edge case. If the OPP
* associated with an MPCC might change due to plane additions, this function
* returns true.
*
* Return:
* Return true if OPP and MPCC might change, otherwise, return false.
*/
static bool could_mpcc_tree_change_for_active_pipes(struct dc *dc,
struct dc_stream_state *stream,
struct dc_surface_update *srf_updates,
int surface_count,
bool *is_plane_addition)
{
(void)srf_updates;
struct dc_stream_status *cur_stream_status = stream_get_status(dc->current_state, stream);
bool force_minimal_pipe_splitting = false;
bool subvp_active = false;
uint32_t i;
*is_plane_addition = false;
if (cur_stream_status &&
dc->current_state->stream_count > 0 &&
dc->debug.pipe_split_policy != MPC_SPLIT_AVOID) {
/* determine if minimal transition is required due to MPC*/
if (surface_count > 0) {
if (cur_stream_status->plane_count > surface_count) {
force_minimal_pipe_splitting = true;
} else if (cur_stream_status->plane_count < surface_count) {
force_minimal_pipe_splitting = true;
*is_plane_addition = true;
}
}
}
if (cur_stream_status &&
dc->current_state->stream_count == 1 &&
dc->debug.enable_single_display_2to1_odm_policy) {
/* determine if minimal transition is required due to dynamic ODM*/
if (surface_count > 0) {
if (cur_stream_status->plane_count > 2 && cur_stream_status->plane_count > surface_count) {
force_minimal_pipe_splitting = true;
} else if (surface_count > 2 && cur_stream_status->plane_count < surface_count) {
force_minimal_pipe_splitting = true;
*is_plane_addition = true;
}
}
}
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
if (dc_state_get_pipe_subvp_type(dc->current_state, pipe) != SUBVP_NONE) {
subvp_active = true;
break;
}
}
/* For SubVP when adding or removing planes we need to add a minimal transition
* (even when disabling all planes). Whenever disabling a phantom pipe, we
* must use the minimal transition path to disable the pipe correctly.
*
* We want to use the minimal transition whenever subvp is active, not only if
* a plane is being added / removed from a subvp stream (MPO plane can be added
* to a DRR pipe of SubVP + DRR config, in which case we still want to run through
* a min transition to disable subvp.
*/
if (cur_stream_status && subvp_active) {
/* determine if minimal transition is required due to SubVP*/
if (cur_stream_status->plane_count > surface_count) {
force_minimal_pipe_splitting = true;
} else if (cur_stream_status->plane_count < surface_count) {
force_minimal_pipe_splitting = true;
*is_plane_addition = true;
}
}
return force_minimal_pipe_splitting;
}
static void release_minimal_transition_state(struct dc *dc,
struct dc_state *minimal_transition_context,
struct dc_state *base_context,
struct pipe_split_policy_backup *policy)
{
restore_minimal_pipe_split_policy(dc, base_context, policy);
dc_state_release(minimal_transition_context);
}
static void force_vsync_flip_in_minimal_transition_context(struct dc_state *context)
{
uint8_t i;
int j;
struct dc_stream_status *stream_status;
for (i = 0; i < context->stream_count; i++) {
stream_status = &context->stream_status[i];
for (j = 0; j < stream_status->plane_count; j++)
stream_status->plane_states[j]->flip_immediate = false;
}
}
static struct dc_state *create_minimal_transition_state(struct dc *dc,
struct dc_state *base_context, struct pipe_split_policy_backup *policy)
{
struct dc_state *minimal_transition_context = NULL;
minimal_transition_context = dc_state_create_copy(base_context);
if (!minimal_transition_context)
return NULL;
backup_and_set_minimal_pipe_split_policy(dc, base_context, policy);
/* commit minimal state */
if (dc->res_pool->funcs->validate_bandwidth(dc, minimal_transition_context,
DC_VALIDATE_MODE_AND_PROGRAMMING) == DC_OK) {
/* prevent underflow and corruption when reconfiguring pipes */
force_vsync_flip_in_minimal_transition_context(minimal_transition_context);
} else {
/*
* This should never happen, minimal transition state should
* always be validated first before adding pipe split features.
*/
release_minimal_transition_state(dc, minimal_transition_context, base_context, policy);
BREAK_TO_DEBUGGER();
minimal_transition_context = NULL;
}
return minimal_transition_context;
}
static bool is_pipe_topology_transition_seamless_with_intermediate_step(
struct dc *dc,
struct dc_state *initial_state,
struct dc_state *intermediate_state,
struct dc_state *final_state)
{
return dc->hwss.is_pipe_topology_transition_seamless(dc, initial_state,
intermediate_state) &&
dc->hwss.is_pipe_topology_transition_seamless(dc,
intermediate_state, final_state);
}
static void swap_and_release_current_context(struct dc *dc,
struct dc_state *new_context, struct dc_stream_state *stream)
{
unsigned int i;
struct dc_state *old = dc->current_state;
struct pipe_ctx *pipe_ctx;
/* Since memory free requires elevated IRQ, an interrupt
* request is generated by mem free. If this happens
* between freeing and reassigning the context, our vsync
* interrupt will call into dc and cause a memory
* corruption. Hence, we first reassign the context,
* then free the old context.
*/
dc->current_state = new_context;
dc_state_release(old);
// clear any forced full updates
for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_ctx = &new_context->res_ctx.pipe_ctx[i];
if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
pipe_ctx->plane_state->force_full_update = false;
}
}
static int initialize_empty_surface_updates(
struct dc_stream_state *stream,
struct dc_surface_update *srf_updates)
{
struct dc_stream_status *status = dc_stream_get_status(stream);
int i;
if (!status)
return 0;
for (i = 0; i < status->plane_count; i++)
srf_updates[i].surface = status->plane_states[i];
return status->plane_count;
}
static bool commit_minimal_transition_based_on_new_context(struct dc *dc,
struct dc_state *new_context,
struct dc_stream_state *stream,
struct dc_stream_update *stream_update,
struct dc_surface_update *srf_updates,
int surface_count)
{
bool success = false;
struct pipe_split_policy_backup policy;
struct dc_state *intermediate_context =
create_minimal_transition_state(dc, new_context,
&policy);
if (intermediate_context) {
if (is_pipe_topology_transition_seamless_with_intermediate_step(
dc,
dc->current_state,
intermediate_context,
new_context)) {
DC_LOG_DC("commit minimal transition state: base = new state\n");
commit_planes_for_stream(dc, srf_updates,
surface_count, stream, stream_update,
UPDATE_TYPE_FULL, intermediate_context);
swap_and_release_current_context(
dc, intermediate_context, stream);
dc_state_retain(dc->current_state);
success = true;
}
release_minimal_transition_state(
dc, intermediate_context, new_context, &policy);
}
return success;
}
static bool commit_minimal_transition_based_on_current_context(struct dc *dc,
struct dc_state *new_context, struct dc_stream_state *stream)
{
bool success = false;
struct pipe_split_policy_backup policy;
struct dc_state *intermediate_context;
struct dc_state *old_current_state = dc->current_state;
struct dc_surface_update srf_updates[MAX_SURFACES] = {0};
int surface_count;
/*
* Both current and new contexts share the same stream and plane state
* pointers. When new context is validated, stream and planes get
* populated with new updates such as new plane addresses. This makes
* the current context no longer valid because stream and planes are
* modified from the original. We backup current stream and plane states
* into scratch space whenever we are populating new context. So we can
* restore the original values back by calling the restore function now.
* This restores back the original stream and plane states associated
* with the current state.
*/
restore_planes_and_stream_state(&dc->scratch.current_state, stream);
dc_state_retain(old_current_state);
intermediate_context = create_minimal_transition_state(dc,
old_current_state, &policy);
if (intermediate_context) {
if (is_pipe_topology_transition_seamless_with_intermediate_step(
dc,
dc->current_state,
intermediate_context,
new_context)) {
DC_LOG_DC("commit minimal transition state: base = current state\n");
surface_count = initialize_empty_surface_updates(
stream, srf_updates);
commit_planes_for_stream(dc, srf_updates,
surface_count, stream, NULL,
UPDATE_TYPE_FULL, intermediate_context);
swap_and_release_current_context(
dc, intermediate_context, stream);
dc_state_retain(dc->current_state);
success = true;
}
release_minimal_transition_state(dc, intermediate_context,
old_current_state, &policy);
}
dc_state_release(old_current_state);
/*
* Restore stream and plane states back to the values associated with
* new context.
*/
restore_planes_and_stream_state(&dc->scratch.new_state, stream);
return success;
}
/**
* commit_minimal_transition_state_in_dc_update - Commit a minimal state based
* on current or new context
*
* @dc: DC structure, used to get the current state
* @new_context: New context
* @stream: Stream getting the update for the flip
* @srf_updates: Surface updates
* @surface_count: Number of surfaces
*
* The function takes in current state and new state and determine a minimal
* transition state as the intermediate step which could make the transition
* between current and new states seamless. If found, it will commit the minimal
* transition state and update current state to this minimal transition state
* and return true, if not, it will return false.
*
* Return:
* Return True if the minimal transition succeeded, false otherwise
*/
static bool commit_minimal_transition_state_in_dc_update(struct dc *dc,
struct dc_state *new_context,
struct dc_stream_state *stream,
struct dc_surface_update *srf_updates,
int surface_count)
{
bool success = commit_minimal_transition_based_on_new_context(
dc, new_context, stream, NULL,
srf_updates, surface_count);
if (!success)
success = commit_minimal_transition_based_on_current_context(dc,
new_context, stream);
if (!success)
DC_LOG_ERROR("Fail to commit a seamless minimal transition state between current and new states.\nThis pipe topology update is non-seamless!\n");
return success;
}
/**
* commit_minimal_transition_state - Create a transition pipe split state
*
* @dc: Used to get the current state status
* @transition_base_context: New transition state
*
* In some specific configurations, such as pipe split on multi-display with
* MPO and/or Dynamic ODM, removing a plane may cause unsupported pipe
* programming when moving to new planes. To mitigate those types of problems,
* this function adds a transition state that minimizes pipe usage before
* programming the new configuration. When adding a new plane, the current
* state requires the least pipes, so it is applied without splitting. When
* removing a plane, the new state requires the least pipes, so it is applied
* without splitting.
*
* Return:
* Return false if something is wrong in the transition state.
*/
static bool commit_minimal_transition_state(struct dc *dc,
struct dc_state *transition_base_context)
{
struct dc_state *transition_context;
struct pipe_split_policy_backup policy;
enum dc_status ret = DC_ERROR_UNEXPECTED;
unsigned int i, j;
unsigned int pipe_in_use = 0;
bool subvp_in_use = false;
bool odm_in_use = false;
/* check current pipes in use*/
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = &transition_base_context->res_ctx.pipe_ctx[i];
if (pipe->plane_state)
pipe_in_use++;
}
/* If SubVP is enabled and we are adding or removing planes from any main subvp
* pipe, we must use the minimal transition.
*/
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
if (pipe->stream && dc_state_get_pipe_subvp_type(dc->current_state, pipe) == SUBVP_PHANTOM) {
subvp_in_use = true;
break;
}
}
/* If ODM is enabled and we are adding or removing planes from any ODM
* pipe, we must use the minimal transition.
*/
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = &transition_base_context->res_ctx.pipe_ctx[i];
if (resource_is_pipe_type(pipe, OTG_MASTER)) {
odm_in_use = resource_get_odm_slice_count(pipe) > 1;
break;
}
}
/* When the OS add a new surface if we have been used all of pipes with odm combine
* and mpc split feature, it need use commit_minimal_transition_state to transition safely.
* After OS exit MPO, it will back to use odm and mpc split with all of pipes, we need
* call it again. Otherwise return true to skip.
*
* Reduce the scenarios to use dc_commit_state_no_check in the stage of flip. Especially
* enter/exit MPO when DCN still have enough resources.
*/
if (pipe_in_use != dc->res_pool->pipe_count && !subvp_in_use && !odm_in_use)
return true;
DC_LOG_DC("%s base = %s state, reason = %s\n", __func__,
dc->current_state == transition_base_context ? "current" : "new",
subvp_in_use ? "Subvp In Use" :
odm_in_use ? "ODM in Use" :
dc->debug.pipe_split_policy != MPC_SPLIT_AVOID ? "MPC in Use" :
"Unknown");
dc_state_retain(transition_base_context);
transition_context = create_minimal_transition_state(dc,
transition_base_context, &policy);
if (transition_context) {
ret = dc_commit_state_no_check(dc, transition_context);
release_minimal_transition_state(dc, transition_context, transition_base_context, &policy);
}
dc_state_release(transition_base_context);
if (ret != DC_OK) {
/* this should never happen */
BREAK_TO_DEBUGGER();
return false;
}
/* force full surface update */
for (i = 0; i < dc->current_state->stream_count; i++) {
for (j = 0; j < (unsigned int)dc->current_state->stream_status[i].plane_count; j++) {
dc_pipe_update_bits_set_full(&dc->current_state->stream_status[i].plane_states[j]->update_bits);
}
}
return true;
}
void populate_fast_updates(struct dc_fast_update *fast_update,
struct dc_surface_update *srf_updates,
int surface_count,
struct dc_stream_update *stream_update)
{
int i = 0;
if (stream_update) {
fast_update[0].out_transfer_func = stream_update->out_transfer_func;
fast_update[0].output_csc_transform = stream_update->output_csc_transform;
fast_update[0].cursor_attributes = stream_update->cursor_attributes;
fast_update[0].cursor_position = stream_update->cursor_position;
fast_update[0].periodic_interrupt = stream_update->periodic_interrupt;
fast_update[0].dither_option = stream_update->dither_option;
fast_update[0].gamut_remap = stream_update->gamut_remap;
fast_update[0].vrr_infopacket = stream_update->vrr_infopacket;
fast_update[0].vsc_infopacket = stream_update->vsc_infopacket;
fast_update[0].vsp_infopacket = stream_update->vsp_infopacket;
fast_update[0].hfvsif_infopacket = stream_update->hfvsif_infopacket;
fast_update[0].vtem_infopacket = stream_update->vtem_infopacket;
fast_update[0].adaptive_sync_infopacket = stream_update->adaptive_sync_infopacket;
fast_update[0].avi_infopacket = stream_update->avi_infopacket;
fast_update[0].hdr_static_metadata = stream_update->hdr_static_metadata;
} else {
fast_update[0].out_transfer_func = NULL;
fast_update[0].output_csc_transform = NULL;
fast_update[0].cursor_attributes = NULL;
fast_update[0].cursor_position = NULL;
fast_update[0].periodic_interrupt = NULL;
fast_update[0].dither_option = NULL;
fast_update[0].gamut_remap = NULL;
fast_update[0].vrr_infopacket = NULL;
fast_update[0].vsc_infopacket = NULL;
fast_update[0].vsp_infopacket = NULL;
fast_update[0].hfvsif_infopacket = NULL;
fast_update[0].vtem_infopacket = NULL;
fast_update[0].adaptive_sync_infopacket = NULL;
fast_update[0].avi_infopacket = NULL;
fast_update[0].hdr_static_metadata = NULL;
}
for (i = 0; i < surface_count; i++) {
fast_update[i].flip_addr = srf_updates[i].flip_addr;
fast_update[i].gamma = srf_updates[i].gamma;
fast_update[i].gamut_remap_matrix = srf_updates[i].gamut_remap_matrix;
fast_update[i].input_csc_color_matrix = srf_updates[i].input_csc_color_matrix;
fast_update[i].coeff_reduction_factor = srf_updates[i].coeff_reduction_factor;
fast_update[i].cursor_csc_color_matrix = srf_updates[i].cursor_csc_color_matrix;
fast_update[i].cm_hist_control = srf_updates[i].cm_hist_control;
}
}
static bool fast_updates_exist(const struct dc_fast_update *fast_update, int surface_count)
{
int i;
if (fast_update[0].out_transfer_func ||
fast_update[0].output_csc_transform ||
fast_update[0].cursor_attributes ||
fast_update[0].cursor_position ||
fast_update[0].periodic_interrupt ||
fast_update[0].dither_option ||
fast_update[0].gamut_remap ||
fast_update[0].vrr_infopacket ||
fast_update[0].vsc_infopacket ||
fast_update[0].vsp_infopacket ||
fast_update[0].hfvsif_infopacket ||
fast_update[0].vtem_infopacket ||
fast_update[0].adaptive_sync_infopacket ||
fast_update[0].avi_infopacket ||
fast_update[0].hdr_static_metadata)
return true;
for (i = 0; i < surface_count; i++) {
if (fast_update[i].flip_addr ||
fast_update[i].gamma ||
fast_update[i].gamut_remap_matrix ||
fast_update[i].input_csc_color_matrix ||
fast_update[i].cursor_csc_color_matrix ||
fast_update[i].cm_hist_control ||
fast_update[i].coeff_reduction_factor)
return true;
}
return false;
}
bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count)
{
int i;
if (fast_update[0].out_transfer_func ||
fast_update[0].output_csc_transform ||
fast_update[0].gamut_remap ||
fast_update[0].cursor_attributes ||
fast_update[0].cursor_position ||
fast_update[0].periodic_interrupt ||
fast_update[0].dither_option ||
fast_update[0].vrr_infopacket ||
fast_update[0].vsc_infopacket ||
fast_update[0].vsp_infopacket ||
fast_update[0].hfvsif_infopacket ||
fast_update[0].vtem_infopacket ||
fast_update[0].adaptive_sync_infopacket ||
fast_update[0].avi_infopacket ||
fast_update[0].hdr_static_metadata)
return true;
for (i = 0; i < surface_count; i++) {
if (fast_update[i].input_csc_color_matrix ||
fast_update[i].gamma ||
fast_update[i].gamut_remap_matrix ||
fast_update[i].coeff_reduction_factor ||
fast_update[i].cm_hist_control ||
fast_update[i].cursor_csc_color_matrix)
return true;
}
return false;
}
static bool full_update_required_weak(
const struct dc *dc,
const struct dc_surface_update *srf_updates,
int surface_count,
const struct dc_stream_update *stream_update,
const struct dc_stream_state *stream)
{
(void)stream_update;
const struct dc_state *context = dc->current_state;
if (srf_updates)
for (int i = 0; i < surface_count; i++)
if (!is_surface_in_context(context, srf_updates[i].surface))
return true;
if (stream) {
const struct dc_stream_status *stream_status = dc_stream_get_status_const(stream);
if (stream_status == NULL || stream_status->plane_count != surface_count)
return true;
}
if (dc->idle_optimizations_allowed)
return true;
if (dc_can_clear_cursor_limit(dc))
return true;
return false;
}
static bool full_update_required(
const struct dc *dc,
const struct dc_surface_update *srf_updates,
int surface_count,
const struct dc_stream_update *stream_update,
const struct dc_stream_state *stream)
{
if (full_update_required_weak(dc, srf_updates, surface_count, stream_update, stream))
return true;
for (int i = 0; i < surface_count; i++) {
if (srf_updates &&
(srf_updates[i].plane_info ||
srf_updates[i].scaling_info ||
(srf_updates[i].hdr_mult.value &&
srf_updates[i].hdr_mult.value != srf_updates->surface->hdr_mult.value) ||
(srf_updates[i].sdr_white_level_nits &&
srf_updates[i].sdr_white_level_nits != srf_updates->surface->sdr_white_level_nits) ||
srf_updates[i].in_transfer_func ||
srf_updates[i].surface->force_full_update ||
(srf_updates[i].flip_addr &&
srf_updates[i].flip_addr->address.tmz_surface != srf_updates[i].surface->address.tmz_surface)))
return true;
}
if (stream_update &&
(((stream_update->src.height != 0 && stream_update->src.width != 0) ||
(stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
stream_update->integer_scaling_update) ||
stream_update->abm_level ||
stream_update->dpms_off ||
stream_update->allow_freesync ||
stream_update->vrr_active_variable ||
stream_update->vrr_active_fixed ||
stream_update->output_color_space ||
stream_update->wb_update ||
stream_update->dsc_config ||
stream_update->mst_bw_update ||
stream_update->func_shaper ||
stream_update->lut3d_func ||
stream_update->pending_test_pattern ||
stream_update->crtc_timing_adjust ||
stream_update->scaler_sharpener_update ||
stream_update->hw_cursor_req))
return true;
return false;
}
static bool fast_update_only(
const struct dc *dc,
const struct dc_fast_update *fast_update,
const struct dc_surface_update *srf_updates,
int surface_count,
const struct dc_stream_update *stream_update,
const struct dc_stream_state *stream)
{
return fast_updates_exist(fast_update, surface_count)
&& !full_update_required(dc, srf_updates, surface_count, stream_update, stream);
}
static bool update_planes_and_stream_v2(struct dc *dc,
struct dc_surface_update *srf_updates, int surface_count,
struct dc_stream_state *stream,
struct dc_stream_update *stream_update)
{
struct dc_state *context;
enum dc_update_type update_type;
struct dc_fast_update fast_update[MAX_SURFACES] = {0};
/* In cases where MPO and split or ODM are used transitions can
* cause underflow. Apply stream configuration with minimal pipe
* split first to avoid unsupported transitions for active pipes.
*/
bool force_minimal_pipe_splitting = 0;
bool is_plane_addition = 0;
bool is_fast_update_only;
populate_fast_updates(fast_update, srf_updates, surface_count, stream_update);
is_fast_update_only = fast_update_only(dc, fast_update, srf_updates,
surface_count, stream_update, stream);
force_minimal_pipe_splitting = could_mpcc_tree_change_for_active_pipes(
dc,
stream,
srf_updates,
surface_count,
&is_plane_addition);
/* on plane addition, minimal state is the current one */
if (force_minimal_pipe_splitting && is_plane_addition &&
!commit_minimal_transition_state(dc, dc->current_state))
return false;
if (!update_planes_and_stream_state(
dc,
srf_updates,
surface_count,
stream,
stream_update,
&update_type,
&context))
return false;
/* on plane removal, minimal state is the new one */
if (force_minimal_pipe_splitting && !is_plane_addition) {
if (!commit_minimal_transition_state(dc, context)) {
dc_state_release(context);
return false;
}
update_type = UPDATE_TYPE_FULL;
}
if (dc->hwss.is_pipe_topology_transition_seamless &&
!dc->hwss.is_pipe_topology_transition_seamless(
dc, dc->current_state, context))
commit_minimal_transition_state_in_dc_update(dc, context, stream,
srf_updates, surface_count);
if (is_fast_update_only && !dc->check_config.enable_legacy_fast_update) {
commit_planes_for_stream_fast(dc,
srf_updates,
surface_count,
stream,
stream_update,
update_type,
context);
} else {
if (!stream_update &&
dc->hwss.is_pipe_topology_transition_seamless &&
!dc->hwss.is_pipe_topology_transition_seamless(
dc, dc->current_state, context)) {
DC_LOG_ERROR("performing non-seamless pipe topology transition with surface only update!\n");
BREAK_TO_DEBUGGER();
}
commit_planes_for_stream(
dc,
srf_updates,
surface_count,
stream,
stream_update,
update_type,
context);
}
if (dc->current_state != context)
swap_and_release_current_context(dc, context, stream);
return true;
}
static void commit_planes_and_stream_update_on_current_context(struct dc *dc,
struct dc_surface_update *srf_updates, int surface_count,
struct dc_stream_state *stream,
struct dc_stream_update *stream_update,
enum dc_update_type update_type)
{
struct dc_fast_update fast_update[MAX_SURFACES] = {0};
ASSERT(update_type < UPDATE_TYPE_FULL);
populate_fast_updates(fast_update, srf_updates, surface_count,
stream_update);
if (fast_update_only(dc, fast_update, srf_updates, surface_count,
stream_update, stream) &&
!dc->check_config.enable_legacy_fast_update)
commit_planes_for_stream_fast(dc,
srf_updates,
surface_count,
stream,
stream_update,
update_type,
dc->current_state);
else
commit_planes_for_stream(
dc,
srf_updates,
surface_count,
stream,
stream_update,
update_type,
dc->current_state);
}
static void commit_planes_and_stream_update_with_new_context(struct dc *dc,
struct dc_surface_update *srf_updates, int surface_count,
struct dc_stream_state *stream,
struct dc_stream_update *stream_update,
enum dc_update_type update_type,
struct dc_state *new_context)
{
bool skip_new_context = false;
ASSERT(update_type >= UPDATE_TYPE_FULL);
/*
* It is required by the feature design that all pipe topologies
* using extra free pipes for power saving purposes such as
* dynamic ODM or SubVp shall only be enabled when it can be
* transitioned seamlessly to AND from its minimal transition
* state. A minimal transition state is defined as the same dc
* state but with all power saving features disabled. So it uses
* the minimum pipe topology. When we can't seamlessly
* transition from state A to state B, we will insert the
* minimal transition state A' or B' in between so seamless
* transition between A and B can be made possible.
*
* To optimize for the time it takes to execute flips,
* the transition from the minimal state to the final state is
* deferred until a steady state (no more transitions) is reached.
*/
if (!dc->hwss.is_pipe_topology_transition_seamless(dc, dc->current_state, new_context)) {
if (!dc->debug.disable_deferred_minimal_transitions) {
dc->check_config.deferred_transition_state = true;
dc->check_config.transition_countdown_to_steady_state =
dc->debug.num_fast_flips_to_steady_state_override ?
dc->debug.num_fast_flips_to_steady_state_override :
NUM_FAST_FLIPS_TO_STEADY_STATE;
if (commit_minimal_transition_based_on_new_context(dc, new_context, stream, stream_update,
srf_updates, surface_count)) {
skip_new_context = true;
dc_state_release(new_context);
new_context = dc->current_state;
} else {
/*
* In this case a new mpo plane is being enabled on pipes that were
* previously in use, and the surface update to the existing plane
* includes an alpha box where the new plane will be, so the update
* from minimal to final cannot be deferred as the alpha box would
* be visible to the user
*/
commit_minimal_transition_based_on_current_context(dc, new_context, stream);
}
} else {
commit_minimal_transition_state_in_dc_update(dc, new_context, stream,
srf_updates, surface_count);
}
} else if (dc->check_config.deferred_transition_state) {
/* reset countdown as steady state not reached */
dc->check_config.transition_countdown_to_steady_state =
dc->debug.num_fast_flips_to_steady_state_override ?
dc->debug.num_fast_flips_to_steady_state_override :
NUM_FAST_FLIPS_TO_STEADY_STATE;
}
if (!skip_new_context) {
commit_planes_for_stream(dc, srf_updates, surface_count, stream, stream_update, update_type, new_context);
swap_and_release_current_context(dc, new_context, stream);
}
}
static bool update_planes_and_stream_v3(struct dc *dc,
struct dc_surface_update *srf_updates, int surface_count,
struct dc_stream_state *stream,
struct dc_stream_update *stream_update)
{
struct dc_state *new_context;
enum dc_update_type update_type;
/*
* When this function returns true and new_context is not equal to
* current state, the function allocates and validates a new dc state
* and assigns it to new_context. The function expects that the caller
* is responsible to free this memory when new_context is no longer
* used. We swap current with new context and free current instead. So
* new_context's memory will live until the next full update after it is
* replaced by a newer context. Refer to the use of
* swap_and_free_current_context below.
*/
if (!update_planes_and_stream_state(dc, srf_updates, surface_count,
stream, stream_update, &update_type,
&new_context))
return false;
if (new_context == dc->current_state) {
commit_planes_and_stream_update_on_current_context(dc,
srf_updates, surface_count, stream,
stream_update, update_type);
if (dc->check_config.transition_countdown_to_steady_state)
dc->check_config.transition_countdown_to_steady_state--;
} else {
commit_planes_and_stream_update_with_new_context(dc,
srf_updates, surface_count, stream,
stream_update, update_type, new_context);
}
return true;
}
static void clear_update_bits(struct dc_surface_update *srf_updates,
int surface_count, struct dc_stream_state *stream)
{
int i;
if (stream)
stream_update_flags_clear(&stream->update_flags);
for (i = 0; i < surface_count; i++)
if (srf_updates[i].surface)
dc_pipe_update_bits_clear(&srf_updates[i].surface->update_bits);
}
static struct dc_update_scratch_space *dc_update_scratch_acquire(struct dc *dc)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(dc->update_scratch_pool); i++) {
if (dc->update_scratch_in_use[i])
continue;
dc->update_scratch_in_use[i] = true;
return dc->update_scratch_pool[i];
}
/* TODO: add recoverable scratch acquisition failure handling. */
ASSERT(false);
return NULL;
}
static void dc_update_scratch_release(struct dc *dc,
struct dc_update_scratch_space *scratch)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(dc->update_scratch_pool); i++) {
if (dc->update_scratch_pool[i] == scratch) {
dc->update_scratch_in_use[i] = false;
return;
}
}
}
/**
* dc_update_state - Commit an absolute dc_state_update.
* @dc: DC structure
* @updates: root update object carrying stream, plane, and probe updates
* Return: true on success, false on failure.
*/
bool dc_update_state(struct dc *dc, const struct dc_state_update *updates)
{
struct dc_update_scratch_space *scratch;
bool more = true;
if (!dc || !updates)
return false;
scratch = dc_update_state_init(dc, updates);
if (!scratch)
return false;
while (more) {
if (!dc_update_state_prepare(scratch))
return false;
dc_update_state_execute(scratch);
more = dc_update_state_cleanup(scratch);
}
return true;
}
/**
* dc_update_planes_and_stream - Shim for dc_update_state.
* @dc: DC structure
* @srf_updates: array of surface update descriptors
* @surface_count: number of entries in @srf_updates
* @stream: target stream
* @stream_update: optional stream update
*
* Packs the individual arguments into a dc_state_update and forwards to
* dc_update_state(). Preserved for out-of-tree and incremental callers.
*
* Return: true on success; false on failure.
*/
bool dc_update_planes_and_stream(struct dc *dc,
struct dc_surface_update *srf_updates, int surface_count,
struct dc_stream_state *stream,
struct dc_stream_update *stream_update)
{
struct dc_state_update updates = {
.stream = stream,
.stream_update = stream_update,
.surface_updates = srf_updates,
.surface_count = surface_count,
};
return dc_update_state(dc, &updates);
}
void dc_commit_updates_for_stream(struct dc *dc,
struct dc_surface_update *srf_updates,
int surface_count,
struct dc_stream_state *stream,
struct dc_stream_update *stream_update,
struct dc_state *state)
{
(void)state;
bool ret = false;
dc_exit_ips_for_hw_access(dc);
/* TODO: Since change commit sequence can have a huge impact,
* we decided to only enable it for DCN3x. However, as soon as
* we get more confident about this change we'll need to enable
* the new sequence for all ASICs.
*/
if (dc->ctx->dce_version >= DCN_VERSION_4_01) {
ret = update_planes_and_stream_v3(dc, srf_updates, surface_count,
stream, stream_update);
} else {
ret = update_planes_and_stream_v2(dc, srf_updates, surface_count,
stream, stream_update);
}
if (ret && dc->ctx->dce_version >= DCN_VERSION_3_2)
clear_update_bits(srf_updates, surface_count, stream);
}
uint8_t dc_get_current_stream_count(struct dc *dc)
{
return dc->current_state->stream_count;
}
struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
{
if (i < dc->current_state->stream_count)
return dc->current_state->streams[i];
return NULL;
}
enum dc_irq_source dc_interrupt_to_irq_source(
struct dc *dc,
uint32_t src_id,
uint32_t ext_id)
{
return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
}
/*
* dc_interrupt_set() - Enable/disable an AMD hw interrupt source
*/
bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
{
if (dc == NULL)
return false;
return dal_irq_service_set(dc->res_pool->irqs, src, enable);
}
void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
{
dal_irq_service_ack(dc->res_pool->irqs, src);
}
/* Preserve this tg if a physical link is still lighting a present display */
static bool should_preserve_tg(struct dc *dc, struct timing_generator *tg)
{
unsigned int i, j;
/* Check if a physical link is lighting this tg */
for (i = 0; i < dc->link_count; i++) {
struct dc_link *link = dc->links[i];
int fe;
if (!link || link->ep_type != DISPLAY_ENDPOINT_PHY ||
!link->link_enc ||
!link->link_enc->funcs->is_dig_enabled ||
!link->link_enc->funcs->is_dig_enabled(link->link_enc) ||
!link->link_enc->funcs->get_dig_frontend)
continue;
/* Get the DIG front-end this link's encoder drives; skip if none */
fe = link->link_enc->funcs->get_dig_frontend(link->link_enc);
if (fe == ENGINE_ID_UNKNOWN)
continue;
/* Find the stream encoder bound to this link's front-end */
for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
struct stream_encoder *se = dc->res_pool->stream_enc[j];
/* Skip unless this stream encoder feeds our front-end and drives this tg */
if (se->id != fe || !se->funcs->dig_source_otg ||
(int)se->funcs->dig_source_otg(se) != tg->inst)
continue;
/* This link drives the OTG: keep a seamless-boot eDP, or
* any external link whose sink is still connected.
*/
if (link->connector_signal == SIGNAL_TYPE_EDP)
return true;
if (link->link_enc->funcs->get_hpd_state &&
dc->link_srv->get_hpd_state(link))
return true;
}
}
return false;
}
/*
* GOP/vBIOS may leave an OPTC enabled for a display present at power-on but no
* longer driven (e.g. external DP unplugged at boot). Such a dangling pipe keeps
* DCN out of idle and blocks s0i3. If nothing needs to survive (no committed
* stream or seamless-boot eDP) and no sink is still connected, power down all hw
* blocks.
*/
void dc_disable_dangling_timing_generators(struct dc *dc)
{
struct dce_hwseq *hws = dc->hwseq;
bool any_dangling = false;
bool any_preserved = false;
bool any_connected = false;
unsigned int i;
/* No real hw to touch on a virtual/emulated environment */
if (dc->ctx->dce_environment == DCE_ENV_VIRTUAL_HW)
return;
/* Wake hw out of IPS before reading/touching tg state */
dc_exit_ips_for_hw_access(dc);
/* Classify every enabled tg as either to-preserve or dangling */
for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
struct timing_generator *tg = dc->res_pool->timing_generators[i];
if (!tg || !tg->funcs->is_tg_enabled ||
!tg->funcs->is_tg_enabled(tg))
continue;
if (should_preserve_tg(dc, tg))
any_preserved = true;
else
any_dangling = true;
}
/* A physically connected sink (HPD asserted) will be re-lit by a
* subsequent atomic commit. For that case we don't call the global
* power_down().
*/
for (i = 0; i < dc->link_count; i++) {
struct dc_link *link = dc->links[i];
if (link && link->ep_type == DISPLAY_ENDPOINT_PHY &&
link->link_enc && link->link_enc->funcs &&
link->link_enc->funcs->get_hpd_state &&
dc->link_srv->get_hpd_state(link)) {
any_connected = true;
break;
}
}
if (!any_dangling)
return;
if (!any_preserved && !any_connected && hws && hws->funcs.power_down) {
/* Truly headless / all sinks unplugged: nothing to preserve */
DC_LOG_DC("%s: powering down dangling hw blocks to allow idle\n",
__func__);
hws->funcs.power_down(dc);
return;
}
}
/*
* dc_get_flip_pending_on_otg() - Check if a GRPH_FLIP is still pending on OTG
*
* @dc: display core context @otg_inst: OTG instance to query
*
* Reads the HUBP flip-pending status for the pipe(s) bound to @otg_inst,
* returning true if any of them has not yet latched its programmed surface
* address.
*
* Unlike dc_plane_get_status(), this does not take or mutate a dc_plane_state,
* so it is safe to call from interrupt context without racing a concurrent
* commit that may be updating plane state.
*
* Return: true if a flip is still pending on the OTG, false otherwise.
*/
bool dc_get_flip_pending_on_otg(struct dc *dc, int otg_inst)
{
bool flip_pending = false;
unsigned int i;
if (!dc || !dc->current_state)
return false;
dc_exit_ips_for_hw_access(dc);
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
struct hubp *hubp = pipe_ctx->plane_res.hubp;
if (!pipe_ctx->plane_state || !pipe_ctx->stream_res.tg)
continue;
if (pipe_ctx->stream_res.tg->inst != otg_inst)
continue;
if (hubp && hubp->funcs->hubp_is_flip_pending &&
hubp->funcs->hubp_is_flip_pending(hubp)) {
flip_pending = true;
break;
}
}
return flip_pending;
}
void dc_power_down_on_boot(struct dc *dc)
{
if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW &&
dc->hwss.power_down_on_boot) {
if (dc->current_state->stream_count > 0)
return;
if (dc->caps.ips_support)
dc_exit_ips_for_hw_access(dc);
dc->hwss.power_down_on_boot(dc);
if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->notify_cstate_disable)
dc->clk_mgr->funcs->notify_cstate_disable(dc->clk_mgr, false);
}
}
void dc_set_power_state(struct dc *dc, enum dc_acpi_cm_power_state power_state)
{
if (!dc->current_state)
return;
dc_exit_ips_for_hw_access(dc);
switch (power_state) {
case DC_ACPI_CM_POWER_STATE_D0:
dc_state_construct(dc, dc->current_state);
dc_z10_restore(dc);
dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, power_state);
dc->hwss.init_hw(dc);
if (dc->hwss.init_sys_ctx != NULL &&
dc->vm_pa_config.valid) {
dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);
}
break;
case DC_ACPI_CM_POWER_STATE_D3:
if (dc->caps.ips_support)
dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3);
if (dc->caps.ips_v2_support) {
if (dc->clk_mgr->funcs->set_low_power_state)
dc->clk_mgr->funcs->set_low_power_state(dc->clk_mgr);
}
break;
default:
ASSERT(dc->current_state->stream_count == 0);
dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, power_state);
dc_state_destruct(dc->current_state);
break;
}
}
void dc_resume(struct dc *dc)
{
uint32_t i;
for (i = 0; i < dc->link_count; i++)
dc->link_srv->resume(dc->links[i]);
}
bool dc_is_dmcu_initialized(struct dc *dc)
{
struct dmcu *dmcu = dc->res_pool->dmcu;
if (dmcu)
return dmcu->funcs->is_dmcu_initialized(dmcu);
return false;
}
enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)
{
if (dc->hwss.set_clock)
return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);
return DC_ERROR_UNEXPECTED;
}
void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)
{
if (dc->hwss.get_clock)
dc->hwss.get_clock(dc, clock_type, clock_cfg);
}
/* enable/disable eDP PSR without specify stream for eDP */
bool dc_set_psr_allow_active(struct dc *dc, bool enable)
{
int i;
bool allow_active;
for (i = 0; i < dc->current_state->stream_count ; i++) {
struct dc_link *link;
struct dc_stream_state *stream = dc->current_state->streams[i];
link = stream->link;
if (!link)
continue;
if (link->psr_settings.psr_feature_enabled) {
if (enable && !link->psr_settings.psr_allow_active) {
allow_active = true;
if (!dc_link_set_psr_allow_active(link, &allow_active, false, false, NULL))
return false;
} else if (!enable && link->psr_settings.psr_allow_active) {
allow_active = false;
if (!dc_link_set_psr_allow_active(link, &allow_active, true, false, NULL))
return false;
}
}
}
return true;
}
/* enable/disable eDP Replay without specify stream for eDP */
bool dc_set_replay_allow_active(struct dc *dc, bool active)
{
int i;
bool allow_active;
for (i = 0; i < dc->current_state->stream_count; i++) {
struct dc_link *link;
struct dc_stream_state *stream = dc->current_state->streams[i];
link = stream->link;
if (!link)
continue;
if (link->replay_settings.replay_feature_enabled) {
if (active && !link->replay_settings.replay_allow_active) {
allow_active = true;
if (!dc_link_set_replay_allow_active(link, &allow_active,
false, false, NULL))
return false;
} else if (!active && link->replay_settings.replay_allow_active) {
allow_active = false;
if (!dc_link_set_replay_allow_active(link, &allow_active,
true, false, NULL))
return false;
}
}
}
return true;
}
/* set IPS disable state */
bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips)
{
dc_exit_ips_for_hw_access(dc);
dc->config.disable_ips = disable_ips;
return true;
}
void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, char const *caller_name)
{
int idle_fclk_khz = 0, idle_dramclk_khz = 0;
unsigned int i = 0;
enum mall_stream_type subvp_pipe_type[MAX_PIPES] = {0};
struct pipe_ctx *pipe = NULL;
struct dc_state *context = dc->current_state;
if (dc->debug.disable_idle_power_optimizations) {
DC_LOG_DEBUG("%s: disabled\n", __func__);
return;
}
if (allow != dc->idle_optimizations_allowed)
DC_LOG_IPS("%s: allow_idle old=%d new=%d (caller=%s)\n", __func__,
dc->idle_optimizations_allowed, allow, caller_name);
if (dc->caps.ips_support && (dc->config.disable_ips == DMUB_IPS_DISABLE_ALL))
return;
if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->is_smu_present)
if (!dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr))
return;
if (allow == dc->idle_optimizations_allowed)
return;
if (dc->hwss.apply_idle_power_optimizations && dc->clk_mgr != NULL &&
dc->hwss.apply_idle_power_optimizations(dc, allow)) {
dc->idle_optimizations_allowed = allow;
DC_LOG_DEBUG("%s: %s\n", __func__, allow ? "enabled" : "disabled");
}
// log idle clocks and sub vp pipe types at idle optimization time
if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->get_hard_min_fclk)
idle_fclk_khz = dc->clk_mgr->funcs->get_hard_min_fclk(dc->clk_mgr);
if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->get_hard_min_memclk)
idle_dramclk_khz = dc->clk_mgr->funcs->get_hard_min_memclk(dc->clk_mgr);
if (dc->res_pool && context) {
for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe = &context->res_ctx.pipe_ctx[i];
subvp_pipe_type[i] = dc_state_get_pipe_subvp_type(context, pipe);
}
}
if (!dc->caps.is_apu)
DC_LOG_DC("%s: allow_idle=%d\n HardMinUClk_Khz=%d HardMinDramclk_Khz=%d\n Pipe_0=%d Pipe_1=%d Pipe_2=%d Pipe_3=%d Pipe_4=%d Pipe_5=%d (caller=%s)\n",
__func__, allow, idle_fclk_khz, idle_dramclk_khz, subvp_pipe_type[0], subvp_pipe_type[1], subvp_pipe_type[2],
subvp_pipe_type[3], subvp_pipe_type[4], subvp_pipe_type[5], caller_name);
}
void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name)
{
if (dc->caps.ips_support)
dc_allow_idle_optimizations_internal(dc, false, caller_name);
}
bool dc_dmub_is_ips_idle_state(struct dc *dc)
{
if (dc->debug.disable_idle_power_optimizations)
return false;
if (!dc->caps.ips_support || (dc->config.disable_ips == DMUB_IPS_DISABLE_ALL))
return false;
if (!dc->ctx->dmub_srv)
return false;
return dc->ctx->dmub_srv->idle_allowed;
}
/* set min and max memory clock to lowest and highest DPM level, respectively */
void dc_unlock_memory_clock_frequency(struct dc *dc)
{
if (dc->clk_mgr->funcs->set_hard_min_memclk)
dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);
if (dc->clk_mgr->funcs->set_hard_max_memclk)
dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
}
/* set min memory clock to the min required for current mode, max to maxDPM */
void dc_lock_memory_clock_frequency(struct dc *dc)
{
if (dc->clk_mgr->funcs->get_memclk_states_from_smu)
dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);
if (dc->clk_mgr->funcs->set_hard_min_memclk)
dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);
if (dc->clk_mgr->funcs->set_hard_max_memclk)
dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
}
static void blank_and_force_memclk(struct dc *dc, bool apply, unsigned int memclk_mhz)
{
(void)apply;
struct dc_state *context = dc->current_state;
struct hubp *hubp;
struct pipe_ctx *pipe;
unsigned int i;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe = &context->res_ctx.pipe_ctx[i];
if (pipe->stream != NULL) {
dc->hwss.disable_pixel_data(dc, pipe, true);
// wait for double buffer
pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VACTIVE);
pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK);
pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VACTIVE);
hubp = pipe->plane_res.hubp;
hubp->funcs->set_blank_regs(hubp, true);
}
}
if (dc->clk_mgr->funcs->set_max_memclk)
dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, memclk_mhz);
if (dc->clk_mgr->funcs->set_min_memclk)
dc->clk_mgr->funcs->set_min_memclk(dc->clk_mgr, memclk_mhz);
for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe = &context->res_ctx.pipe_ctx[i];
if (pipe->stream != NULL) {
dc->hwss.disable_pixel_data(dc, pipe, false);
hubp = pipe->plane_res.hubp;
hubp->funcs->set_blank_regs(hubp, false);
}
}
}
/**
* dc_enable_dcmode_clk_limit() - lower clocks in dc (battery) mode
* @dc: pointer to dc of the dm calling this
* @enable: True = transition to DC mode, false = transition back to AC mode
*
* Some SoCs define additional clock limits when in DC mode, DM should
* invoke this function when the platform undergoes a power source transition
* so DC can apply/unapply the limit. This interface may be disruptive to
* the onscreen content.
*
* Context: Triggered by OS through DM interface, or manually by escape calls.
* Need to hold a dclock when doing so.
*
* Return: none (void function)
*
*/
void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable)
{
unsigned int softMax = 0, maxDPM = 0, funcMin = 0, i;
bool p_state_change_support;
if (!dc->config.dc_mode_clk_limit_support)
return;
softMax = dc->clk_mgr->bw_params->dc_mode_softmax_memclk;
for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries; i++) {
if (dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz > maxDPM)
maxDPM = dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz;
}
funcMin = (dc->clk_mgr->clks.dramclk_khz + 999) / 1000;
p_state_change_support = dc->clk_mgr->clks.p_state_change_support;
if (enable && !dc->clk_mgr->dc_mode_softmax_enabled) {
if (p_state_change_support) {
if (funcMin <= softMax && dc->clk_mgr->funcs->set_max_memclk)
dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, softMax);
// else: No-Op
} else {
if (funcMin <= softMax)
blank_and_force_memclk(dc, true, softMax);
// else: No-Op
}
} else if (!enable && dc->clk_mgr->dc_mode_softmax_enabled) {
if (p_state_change_support) {
if (funcMin <= softMax && dc->clk_mgr->funcs->set_max_memclk)
dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, maxDPM);
// else: No-Op
} else {
if (funcMin <= softMax)
blank_and_force_memclk(dc, true, maxDPM);
// else: No-Op
}
}
dc->clk_mgr->dc_mode_softmax_enabled = enable;
}
bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc,
unsigned int pitch,
unsigned int height,
enum surface_pixel_format format,
struct dc_cursor_attributes *cursor_attr)
{
if (dc->hwss.does_plane_fit_in_mall && dc->hwss.does_plane_fit_in_mall(dc, pitch, height, format, cursor_attr))
return true;
return false;
}
/* cleanup on driver unload */
void dc_hardware_release(struct dc *dc)
{
dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(dc);
if (dc->hwss.hardware_release)
dc->hwss.hardware_release(dc);
}
void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc)
{
if (dc->current_state)
dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down = true;
}
/**
* dc_is_dmub_outbox_supported - Check if DMUB firmware support outbox notification
*
* @dc: [in] dc structure
*
* Checks whether DMUB FW supports outbox notifications, if supported DM
* should register outbox interrupt prior to actually enabling interrupts
* via dc_enable_dmub_outbox
*
* Return:
* True if DMUB FW supports outbox notifications, False otherwise
*/
bool dc_is_dmub_outbox_supported(struct dc *dc)
{
if (!dc->caps.dmcub_support)
return false;
switch (dc->ctx->asic_id.chip_family) {
case FAMILY_YELLOW_CARP:
/* DCN31 B0 USB4 DPIA needs dmub notifications for interrupts */
if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
!dc->debug.dpia_debug.bits.disable_dpia)
return true;
break;
case AMDGPU_FAMILY_GC_11_0_1:
case AMDGPU_FAMILY_GC_11_5_0:
case AMDGPU_FAMILY_GC_11_5_4:
if (!dc->debug.dpia_debug.bits.disable_dpia)
return true;
break;
default:
break;
}
/* dmub aux needs dmub notifications to be enabled */
return dc->debug.enable_dmub_aux_for_legacy_ddc;
}
/**
* dc_enable_dmub_notifications - Check if dmub fw supports outbox
*
* @dc: [in] dc structure
*
* Calls dc_is_dmub_outbox_supported to check if dmub fw supports outbox
* notifications. All DMs shall switch to dc_is_dmub_outbox_supported. This
* API shall be removed after switching.
*
* Return:
* True if DMUB FW supports outbox notifications, False otherwise
*/
bool dc_enable_dmub_notifications(struct dc *dc)
{
return dc_is_dmub_outbox_supported(dc);
}
/**
* dc_enable_dmub_outbox - Enables DMUB unsolicited notification
*
* @dc: [in] dc structure
*
* Enables DMUB unsolicited notifications to x86 via outbox.
*/
void dc_enable_dmub_outbox(struct dc *dc)
{
struct dc_context *dc_ctx = dc->ctx;
dmub_enable_outbox_notification(dc_ctx->dmub_srv);
DC_LOG_DC("%s: dmub outbox notifications enabled\n", __func__);
}
/**
* dc_process_dmub_aux_transfer_async - Submits aux command to dmub via inbox message
* Sets port index appropriately for legacy DDC
* @dc: dc structure
* @link_index: link index
* @payload: aux payload
*
* Returns: True if successful, False if failure
*/
bool dc_process_dmub_aux_transfer_async(struct dc *dc,
uint32_t link_index,
struct aux_payload *payload)
{
uint8_t action;
union dmub_rb_cmd cmd = {0};
if (link_index >= dc->link_count || !dc->links[link_index])
return false;
if (payload->length > sizeof(cmd.dp_aux_access.aux_control.dpaux.data))
return false;
cmd.dp_aux_access.header.type = DMUB_CMD__DP_AUX_ACCESS;
cmd.dp_aux_access.header.payload_bytes = 0;
/* For dpia, ddc_pin is set to NULL */
if (!dc->links[link_index]->ddc->ddc_pin)
cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_DPIA;
else
cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_LEGACY_DDC;
cmd.dp_aux_access.aux_control.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst;
cmd.dp_aux_access.aux_control.sw_crc_enabled = 0;
cmd.dp_aux_access.aux_control.timeout = 0;
cmd.dp_aux_access.aux_control.dpaux.address = payload->address;
cmd.dp_aux_access.aux_control.dpaux.is_i2c_over_aux = payload->i2c_over_aux;
cmd.dp_aux_access.aux_control.dpaux.length = (uint8_t)payload->length;
/* set aux action */
if (payload->i2c_over_aux) {
if (payload->write) {
if (payload->mot)
action = DP_AUX_REQ_ACTION_I2C_WRITE_MOT;
else
action = DP_AUX_REQ_ACTION_I2C_WRITE;
} else {
if (payload->mot)
action = DP_AUX_REQ_ACTION_I2C_READ_MOT;
else
action = DP_AUX_REQ_ACTION_I2C_READ;
}
} else {
if (payload->write)
action = DP_AUX_REQ_ACTION_DPCD_WRITE;
else
action = DP_AUX_REQ_ACTION_DPCD_READ;
}
cmd.dp_aux_access.aux_control.dpaux.action = action;
if (payload->length && payload->write) {
memcpy(cmd.dp_aux_access.aux_control.dpaux.data,
payload->data,
payload->length
);
}
dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
return true;
}
bool dc_smart_power_oled_enable(const struct dc_link *link, bool enable, uint16_t peak_nits,
uint8_t debug_control, uint16_t fixed_CLL, uint32_t triggerline)
{
bool status = false;
struct dc *dc = link->ctx->dc;
union dmub_rb_cmd cmd;
uint8_t otg_inst = 0;
unsigned int panel_inst = 0;
struct pipe_ctx *pipe_ctx = NULL;
struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx;
int i = 0;
// get panel_inst
if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
return status;
// get otg_inst
for (i = 0; i < MAX_PIPES; i++) {
if (res_ctx &&
res_ctx->pipe_ctx[i].stream &&
res_ctx->pipe_ctx[i].stream->link &&
res_ctx->pipe_ctx[i].stream->link == link &&
res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) {
pipe_ctx = &res_ctx->pipe_ctx[i];
//TODO: refactor for multi edp support
break;
}
}
if (pipe_ctx)
otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
// before enable smart power OLED, we need to call set pipe for DMUB to set ABM config
if (enable) {
if (dc->hwss.set_pipe && pipe_ctx)
dc->hwss.set_pipe(pipe_ctx);
}
// fill in cmd
memset(&cmd, 0, sizeof(cmd));
cmd.smart_power_oled_enable.header.type = DMUB_CMD__SMART_POWER_OLED;
cmd.smart_power_oled_enable.header.sub_type = DMUB_CMD__SMART_POWER_OLED_ENABLE;
cmd.smart_power_oled_enable.header.payload_bytes =
sizeof(struct dmub_rb_cmd_smart_power_oled_enable_data) - sizeof(struct dmub_cmd_header);
cmd.smart_power_oled_enable.header.ret_status = 1;
cmd.smart_power_oled_enable.data.enable = enable;
cmd.smart_power_oled_enable.data.panel_inst = (uint8_t)panel_inst;
cmd.smart_power_oled_enable.data.peak_nits = peak_nits;
cmd.smart_power_oled_enable.data.otg_inst = otg_inst;
cmd.smart_power_oled_enable.data.digfe_inst = (uint8_t)link->link_enc->preferred_engine;
cmd.smart_power_oled_enable.data.digbe_inst = (uint8_t)link->link_enc->transmitter;
cmd.smart_power_oled_enable.data.debugcontrol = debug_control;
cmd.smart_power_oled_enable.data.triggerline = triggerline;
cmd.smart_power_oled_enable.data.fixed_max_cll = fixed_CLL;
// send cmd
status = dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
// Update firmware_controlled_hdr_info_packet state on successful command execution
if (status && pipe_ctx)
pipe_ctx->stream->firmware_controlled_hdr_info_packet = enable;
return status;
}
bool dc_smart_power_oled_get_max_cll(const struct dc_link *link, unsigned int *pCurrent_MaxCLL)
{
struct dc *dc = link->ctx->dc;
union dmub_rb_cmd cmd;
bool status = false;
unsigned int panel_inst = 0;
// get panel_inst
if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
return status;
// fill in cmd
memset(&cmd, 0, sizeof(cmd));
cmd.smart_power_oled_getmaxcll.header.type = DMUB_CMD__SMART_POWER_OLED;
cmd.smart_power_oled_getmaxcll.header.sub_type = DMUB_CMD__SMART_POWER_OLED_GETMAXCLL;
cmd.smart_power_oled_getmaxcll.header.payload_bytes = sizeof(cmd.smart_power_oled_getmaxcll.data);
cmd.smart_power_oled_getmaxcll.header.ret_status = 1;
cmd.smart_power_oled_getmaxcll.data.input.panel_inst = (uint8_t)panel_inst;
// send cmd and wait for reply
status = dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);
if (status)
*pCurrent_MaxCLL = cmd.smart_power_oled_getmaxcll.data.output.current_max_cll;
else
*pCurrent_MaxCLL = 0;
return status;
}
uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,
uint8_t dpia_port_index)
{
uint8_t index, link_index = 0xFF;
for (index = 0; index < dc->link_count; index++) {
/* ddc_hw_inst has dpia port index for dpia links
* and ddc instance for legacy links
*/
if (!dc->links[index]->ddc->ddc_pin) {
if (dc->links[index]->ddc_hw_inst == dpia_port_index) {
link_index = index;
break;
}
}
}
ASSERT(link_index != 0xFF);
return link_index;
}
/**
* dc_process_dmub_set_config_async - Submits set_config command
*
* @dc: [in] dc structure
* @link_index: [in] link_index: link index
* @payload: [in] aux payload
* @notify: [out] set_config immediate reply
*
* Submits set_config command to dmub via inbox message.
*
* Return:
* True if successful, False if failure
*/
bool dc_process_dmub_set_config_async(struct dc *dc,
uint32_t link_index,
struct set_config_cmd_payload *payload,
struct dmub_notification *notify)
{
union dmub_rb_cmd cmd = {0};
bool is_cmd_complete = true;
/* prepare SET_CONFIG command */
cmd.set_config_access.header.type = DMUB_CMD__DPIA;
cmd.set_config_access.header.sub_type = DMUB_CMD__DPIA_SET_CONFIG_ACCESS;
cmd.set_config_access.set_config_control.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst;
cmd.set_config_access.set_config_control.cmd_pkt.msg_type = payload->msg_type;
cmd.set_config_access.set_config_control.cmd_pkt.msg_data = payload->msg_data;
if (!dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) {
/* command is not processed by dmub */
notify->sc_status = SET_CONFIG_UNKNOWN_ERROR;
return is_cmd_complete;
}
/* command processed by dmub, if ret_status is 1, it is completed instantly */
if (cmd.set_config_access.header.ret_status == 1)
notify->sc_status = cmd.set_config_access.set_config_control.immed_status;
else
/* cmd pending, will receive notification via outbox */
is_cmd_complete = false;
return is_cmd_complete;
}
/**
* dc_process_dmub_set_mst_slots - Submits MST solt allocation
*
* @dc: [in] dc structure
* @link_index: [in] link index
* @mst_alloc_slots: [in] mst slots to be allotted
* @mst_slots_in_use: [out] mst slots in use returned in failure case
*
* Submits mst slot allocation command to dmub via inbox message
*
* Return:
* DC_OK if successful, DC_ERROR if failure
*/
enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
uint32_t link_index,
uint8_t mst_alloc_slots,
uint8_t *mst_slots_in_use)
{
union dmub_rb_cmd cmd = {0};
/* prepare MST_ALLOC_SLOTS command */
cmd.set_mst_alloc_slots.header.type = DMUB_CMD__DPIA;
cmd.set_mst_alloc_slots.header.sub_type = DMUB_CMD__DPIA_MST_ALLOC_SLOTS;
cmd.set_mst_alloc_slots.mst_slots_control.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst;
cmd.set_mst_alloc_slots.mst_slots_control.mst_alloc_slots = mst_alloc_slots;
if (!dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))
/* command is not processed by dmub */
return DC_ERROR_UNEXPECTED;
/* command processed by dmub, if ret_status is 1 */
if (cmd.set_config_access.header.ret_status != 1)
/* command processing error */
return DC_ERROR_UNEXPECTED;
/* command processed and we have a status of 2, mst not enabled in dpia */
if (cmd.set_mst_alloc_slots.mst_slots_control.immed_status == 2)
return DC_FAIL_UNSUPPORTED_1;
/* previously configured mst alloc and used slots did not match */
if (cmd.set_mst_alloc_slots.mst_slots_control.immed_status == 3) {
*mst_slots_in_use = cmd.set_mst_alloc_slots.mst_slots_control.mst_slots_in_use;
return DC_NOT_SUPPORTED;
}
return DC_OK;
}
/**
* dc_process_dmub_dpia_set_tps_notification - Submits tps notification
*
* @dc: [in] dc structure
* @link_index: [in] link index
* @tps: [in] request tps
*
* Submits set_tps_notification command to dmub via inbox message
*/
void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps)
{
union dmub_rb_cmd cmd = {0};
cmd.set_tps_notification.header.type = DMUB_CMD__DPIA;
cmd.set_tps_notification.header.sub_type = DMUB_CMD__DPIA_SET_TPS_NOTIFICATION;
cmd.set_tps_notification.tps_notification.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst;
cmd.set_tps_notification.tps_notification.tps = tps;
dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
}
/**
* dc_process_dmub_dpia_hpd_int_enable - Submits DPIA DPD interruption
*
* @dc: [in] dc structure
* @hpd_int_enable: [in] 1 for hpd int enable, 0 to disable
*
* Submits dpia hpd int enable command to dmub via inbox message
*/
void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,
uint32_t hpd_int_enable)
{
union dmub_rb_cmd cmd = {0};
cmd.dpia_hpd_int_enable.header.type = DMUB_CMD__DPIA_HPD_INT_ENABLE;
cmd.dpia_hpd_int_enable.enable = hpd_int_enable;
dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
DC_LOG_DEBUG("%s: hpd_int_enable(%d)\n", __func__, hpd_int_enable);
}
/**
* dc_print_dmub_diagnostic_data - Print DMUB diagnostic data for debugging
*
* @dc: [in] dc structure
*
*
*/
void dc_print_dmub_diagnostic_data(const struct dc *dc)
{
dc_dmub_srv_log_diagnostic_data(dc->ctx->dmub_srv);
}
/**
* dc_disable_accelerated_mode - disable accelerated mode
* @dc: dc structure
*/
void dc_disable_accelerated_mode(struct dc *dc)
{
bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 0);
}
/**
* dc_notify_vsync_int_state - notifies vsync enable/disable state
* @dc: dc structure
* @stream: stream where vsync int state changed
* @enable: whether vsync is enabled or disabled
*
* Called when vsync is enabled/disabled Will notify DMUB to start/stop ABM
* interrupts after steady state is reached.
*/
void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable)
{
unsigned int i, edp_num;
struct pipe_ctx *pipe = NULL;
struct dc_link *link = stream->sink->link;
struct dc_link *edp_links[MAX_NUM_EDP];
if (link->psr_settings.psr_feature_enabled)
return;
if (link->replay_settings.replay_feature_enabled)
return;
/*find primary pipe associated with stream*/
for (i = 0; i < MAX_PIPES; i++) {
pipe = &dc->current_state->res_ctx.pipe_ctx[i];
if (pipe->stream == stream && pipe->stream_res.tg)
break;
}
if (i == MAX_PIPES) {
ASSERT(0);
return;
}
dc_get_edp_links(dc, edp_links, &edp_num);
/* Determine panel inst */
for (i = 0; i < edp_num; i++) {
if (edp_links[i] == link)
break;
}
if (i == edp_num) {
return;
}
if (pipe->stream_res.abm && pipe->stream_res.abm->funcs->set_abm_pause)
pipe->stream_res.abm->funcs->set_abm_pause(pipe->stream_res.abm, !enable, i, pipe->stream_res.tg->inst);
}
/*****************************************************************************
* dc_abm_save_restore() - Interface to DC for save+pause and restore+un-pause
* ABM
* @dc: dc structure
* @stream: stream where vsync int state changed
* @pData: abm hw states
*
****************************************************************************/
bool dc_abm_save_restore(
struct dc *dc,
struct dc_stream_state *stream,
struct abm_save_restore *pData)
{
unsigned int i, edp_num;
struct pipe_ctx *pipe = NULL;
struct dc_link *link = stream->sink->link;
struct dc_link *edp_links[MAX_NUM_EDP];
if (link->replay_settings.replay_feature_enabled)
return false;
/*find primary pipe associated with stream*/
for (i = 0; i < MAX_PIPES; i++) {
pipe = &dc->current_state->res_ctx.pipe_ctx[i];
if (pipe->stream == stream && pipe->stream_res.tg)
break;
}
if (i == MAX_PIPES) {
ASSERT(0);
return false;
}
dc_get_edp_links(dc, edp_links, &edp_num);
/* Determine panel inst */
for (i = 0; i < edp_num; i++)
if (edp_links[i] == link)
break;
if (i == edp_num)
return false;
if (pipe->stream_res.abm &&
pipe->stream_res.abm->funcs->save_restore)
return pipe->stream_res.abm->funcs->save_restore(
pipe->stream_res.abm,
i,
pData);
return false;
}
void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties)
{
unsigned int i;
unsigned int max_cursor_size = dc->caps.max_cursor_size;
unsigned int stream_cursor_size;
if (dc->debug.allow_sw_cursor_fallback && dc->res_pool->funcs->get_max_hw_cursor_size) {
for (i = 0; i < dc->current_state->stream_count; i++) {
stream_cursor_size = dc->res_pool->funcs->get_max_hw_cursor_size(dc,
dc->current_state,
dc->current_state->streams[i]);
if (stream_cursor_size < max_cursor_size) {
max_cursor_size = stream_cursor_size;
}
}
}
properties->cursor_size_limit = max_cursor_size;
}
/**
* dc_set_edp_power() - DM controls eDP power to be ON/OFF
*
* Called when DM wants to power on/off eDP.
* Only work on links with flag skip_implict_edp_power_control is set.
*
* @dc: Current DC state
* @edp_link: a link with eDP connector signal type
* @powerOn: power on/off eDP
*
* Return: void
*/
void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link,
bool powerOn)
{
(void)dc;
if (edp_link->connector_signal != SIGNAL_TYPE_EDP)
return;
if (edp_link->skip_implict_edp_power_control == false)
return;
edp_link->dc->link_srv->edp_set_panel_power(edp_link, powerOn);
}
/**
* dc_get_power_profile_for_dc_state() - extracts power profile from dc state
*
* Called when DM wants to make power policy decisions based on dc_state
*
* @context: Pointer to the dc_state from which the power profile is extracted.
*
* Return: The power profile structure containing the power level information.
*/
struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context)
{
struct dc_power_profile profile = { 0 };
profile.power_level = !context->bw_ctx.bw.dcn.clk.p_state_change_support;
if (!context->clk_mgr || !context->clk_mgr->ctx || !context->clk_mgr->ctx->dc)
return profile;
struct dc *dc = context->clk_mgr->ctx->dc;
if (dc->res_pool->funcs->get_power_profile)
profile.power_level = dc->res_pool->funcs->get_power_profile(context);
return profile;
}
/**
* dc_get_det_buffer_size_from_state() - extracts detile buffer size from dc state
*
* This function is called to log the detile buffer size from the dc_state.
*
* @context: a pointer to the dc_state from which the detile buffer size is extracted.
*
* Return: the size of the detile buffer, or 0 if not available.
*/
unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context)
{
struct dc *dc = context->clk_mgr->ctx->dc;
if (dc->res_pool->funcs->get_det_buffer_size)
return dc->res_pool->funcs->get_det_buffer_size(context);
else
return 0;
}
/**
* dc_get_host_router_index: Get index of host router from a dpia link
*
* This function return a host router index of the target link. If the target link is dpia link.
*
* @link: Pointer to the target link (input)
* @host_router_index: Pointer to store the host router index of the target link (output).
*
* Return: true if the host router index is found and valid.
*
*/
bool dc_get_host_router_index(const struct dc_link *link, unsigned int *host_router_index)
{
struct dc *dc;
if (!link || !host_router_index || link->ep_type != DISPLAY_ENDPOINT_USB4_DPIA)
return false;
dc = link->ctx->dc;
if (link->link_index < dc->lowest_dpia_link_index)
return false;
*host_router_index = (link->link_index - dc->lowest_dpia_link_index) / dc->caps.num_of_dpias_per_host_router;
if (*host_router_index < dc->caps.num_of_host_routers)
return true;
else
return false;
}
bool dc_is_cursor_limit_pending(struct dc *dc)
{
uint32_t i;
for (i = 0; i < dc->current_state->stream_count; i++) {
if (dc_stream_is_cursor_limit_pending(dc, dc->current_state->streams[i]))
return true;
}
return false;
}
bool dc_can_clear_cursor_limit(const struct dc *dc)
{
uint32_t i;
for (i = 0; i < dc->current_state->stream_count; i++) {
if (dc_state_can_clear_stream_cursor_subvp_limit(dc->current_state->streams[i], dc->current_state))
return true;
}
return false;
}
void dc_get_underflow_debug_data_for_otg(struct dc *dc, unsigned int primary_otg_inst,
struct dc_underflow_debug_data *out_data)
{
struct timing_generator *tg = NULL;
for (int i = 0; i < MAX_PIPES; i++) {
if (dc->res_pool->timing_generators[i] &&
dc->res_pool->timing_generators[i]->inst == primary_otg_inst) {
tg = dc->res_pool->timing_generators[i];
break;
}
}
dc_exit_ips_for_hw_access(dc);
if (dc->hwss.get_underflow_debug_data)
dc->hwss.get_underflow_debug_data(dc, tg, out_data);
}
void dc_get_power_feature_status(struct dc *dc, unsigned int primary_otg_inst,
struct power_features *out_data)
{
(void)primary_otg_inst;
out_data->uclk_p_state = dc->current_state->clk_mgr->clks.p_state_change_support;
out_data->fams = dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching;
}
bool dc_capture_register_software_state(struct dc *dc, struct dc_register_software_state *state)
{
struct dc_state *context;
struct resource_context *res_ctx;
unsigned int i;
const unsigned int max_pipes = MAX_PIPES;
if (!dc || !dc->current_state || !state) {
if (state)
state->state_valid = false;
return false;
}
/* Initialize the state structure */
memset(state, 0, sizeof(struct dc_register_software_state));
context = dc->current_state;
res_ctx = &context->res_ctx;
/* Count active pipes and streams */
state->active_pipe_count = 0;
state->active_stream_count = context->stream_count;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
if (res_ctx->pipe_ctx[i].stream)
state->active_pipe_count++;
}
/* Capture HUBP programming state for each pipe */
for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
state->hubp[i].valid_stream = false;
if (!pipe_ctx->stream)
continue;
state->hubp[i].valid_stream = true;
/* HUBP register programming variables */
if (pipe_ctx->stream_res.tg)
state->hubp[i].vtg_sel = pipe_ctx->stream_res.tg->inst;
state->hubp[i].hubp_clock_enable = (pipe_ctx->plane_res.hubp != NULL) ? 1 : 0;
state->hubp[i].valid_plane_state = false;
if (pipe_ctx->plane_state) {
state->hubp[i].valid_plane_state = true;
state->hubp[i].surface_pixel_format = pipe_ctx->plane_state->format;
state->hubp[i].rotation_angle = pipe_ctx->plane_state->rotation;
state->hubp[i].h_mirror_en = pipe_ctx->plane_state->horizontal_mirror ? 1 : 0;
/* Surface size */
if (pipe_ctx->plane_state->plane_size.surface_size.width > 0) {
state->hubp[i].surface_size_width = pipe_ctx->plane_state->plane_size.surface_size.width;
state->hubp[i].surface_size_height = pipe_ctx->plane_state->plane_size.surface_size.height;
}
/* Viewport dimensions from scaler data */
if (pipe_ctx->plane_state->src_rect.width > 0) {
state->hubp[i].pri_viewport_width = pipe_ctx->plane_state->src_rect.width;
state->hubp[i].pri_viewport_height = pipe_ctx->plane_state->src_rect.height;
state->hubp[i].pri_viewport_x_start = pipe_ctx->plane_state->src_rect.x;
state->hubp[i].pri_viewport_y_start = pipe_ctx->plane_state->src_rect.y;
}
/* DCC settings */
state->hubp[i].surface_dcc_en = (pipe_ctx->plane_state->dcc.enable) ? 1 : 0;
state->hubp[i].surface_dcc_ind_64b_blk = pipe_ctx->plane_state->dcc.independent_64b_blks;
state->hubp[i].surface_dcc_ind_128b_blk = pipe_ctx->plane_state->dcc.dcc_ind_blk;
/* Surface pitch */
state->hubp[i].surface_pitch = pipe_ctx->plane_state->plane_size.surface_pitch;
state->hubp[i].meta_pitch = pipe_ctx->plane_state->dcc.meta_pitch;
state->hubp[i].chroma_pitch = pipe_ctx->plane_state->plane_size.chroma_pitch;
state->hubp[i].meta_pitch_c = pipe_ctx->plane_state->dcc.meta_pitch_c;
/* Surface addresses - primary */
state->hubp[i].primary_surface_address_low = pipe_ctx->plane_state->address.grph.addr.low_part;
state->hubp[i].primary_surface_address_high = pipe_ctx->plane_state->address.grph.addr.high_part;
state->hubp[i].primary_meta_surface_address_low = pipe_ctx->plane_state->address.grph.meta_addr.low_part;
state->hubp[i].primary_meta_surface_address_high = pipe_ctx->plane_state->address.grph.meta_addr.high_part;
/* TMZ settings */
state->hubp[i].primary_surface_tmz = pipe_ctx->plane_state->address.tmz_surface;
state->hubp[i].primary_meta_surface_tmz = pipe_ctx->plane_state->address.tmz_surface;
/* Tiling configuration */
state->hubp[i].min_dc_gfx_version9 = false;
if (pipe_ctx->plane_state->tiling_info.gfxversion >= DcGfxVersion9) {
state->hubp[i].min_dc_gfx_version9 = true;
state->hubp[i].sw_mode = pipe_ctx->plane_state->tiling_info.gfx9.swizzle;
state->hubp[i].num_pipes = pipe_ctx->plane_state->tiling_info.gfx9.num_pipes;
state->hubp[i].num_banks = pipe_ctx->plane_state->tiling_info.gfx9.num_banks;
state->hubp[i].pipe_interleave = pipe_ctx->plane_state->tiling_info.gfx9.pipe_interleave;
state->hubp[i].num_shader_engines = pipe_ctx->plane_state->tiling_info.gfx9.num_shader_engines;
state->hubp[i].num_rb_per_se = pipe_ctx->plane_state->tiling_info.gfx9.num_rb_per_se;
state->hubp[i].num_pkrs = pipe_ctx->plane_state->tiling_info.gfx9.num_pkrs;
}
}
/* DML Request Size Configuration */
if (pipe_ctx->rq_regs.rq_regs_l.chunk_size > 0) {
state->hubp[i].rq_chunk_size = pipe_ctx->rq_regs.rq_regs_l.chunk_size;
state->hubp[i].rq_min_chunk_size = pipe_ctx->rq_regs.rq_regs_l.min_chunk_size;
state->hubp[i].rq_meta_chunk_size = pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size;
state->hubp[i].rq_min_meta_chunk_size = pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size;
state->hubp[i].rq_dpte_group_size = pipe_ctx->rq_regs.rq_regs_l.dpte_group_size;
state->hubp[i].rq_mpte_group_size = pipe_ctx->rq_regs.rq_regs_l.mpte_group_size;
state->hubp[i].rq_swath_height_l = pipe_ctx->rq_regs.rq_regs_l.swath_height;
state->hubp[i].rq_pte_row_height_l = pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear;
}
/* Chroma request size configuration */
if (pipe_ctx->rq_regs.rq_regs_c.chunk_size > 0) {
state->hubp[i].rq_chunk_size_c = pipe_ctx->rq_regs.rq_regs_c.chunk_size;
state->hubp[i].rq_min_chunk_size_c = pipe_ctx->rq_regs.rq_regs_c.min_chunk_size;
state->hubp[i].rq_meta_chunk_size_c = pipe_ctx->rq_regs.rq_regs_c.meta_chunk_size;
state->hubp[i].rq_min_meta_chunk_size_c = pipe_ctx->rq_regs.rq_regs_c.min_meta_chunk_size;
state->hubp[i].rq_dpte_group_size_c = pipe_ctx->rq_regs.rq_regs_c.dpte_group_size;
state->hubp[i].rq_mpte_group_size_c = pipe_ctx->rq_regs.rq_regs_c.mpte_group_size;
state->hubp[i].rq_swath_height_c = pipe_ctx->rq_regs.rq_regs_c.swath_height;
state->hubp[i].rq_pte_row_height_c = pipe_ctx->rq_regs.rq_regs_c.pte_row_height_linear;
}
/* DML expansion modes */
state->hubp[i].drq_expansion_mode = pipe_ctx->rq_regs.drq_expansion_mode;
state->hubp[i].prq_expansion_mode = pipe_ctx->rq_regs.prq_expansion_mode;
state->hubp[i].mrq_expansion_mode = pipe_ctx->rq_regs.mrq_expansion_mode;
state->hubp[i].crq_expansion_mode = pipe_ctx->rq_regs.crq_expansion_mode;
/* DML DLG parameters - nominal */
state->hubp[i].dst_y_per_vm_vblank = pipe_ctx->dlg_regs.dst_y_per_vm_vblank;
state->hubp[i].dst_y_per_row_vblank = pipe_ctx->dlg_regs.dst_y_per_row_vblank;
state->hubp[i].dst_y_per_vm_flip = pipe_ctx->dlg_regs.dst_y_per_vm_flip;
state->hubp[i].dst_y_per_row_flip = pipe_ctx->dlg_regs.dst_y_per_row_flip;
/* DML prefetch settings */
state->hubp[i].dst_y_prefetch = pipe_ctx->dlg_regs.dst_y_prefetch;
state->hubp[i].vratio_prefetch = pipe_ctx->dlg_regs.vratio_prefetch;
state->hubp[i].vratio_prefetch_c = pipe_ctx->dlg_regs.vratio_prefetch_c;
/* TTU parameters */
state->hubp[i].qos_level_low_wm = pipe_ctx->ttu_regs.qos_level_low_wm;
state->hubp[i].qos_level_high_wm = pipe_ctx->ttu_regs.qos_level_high_wm;
state->hubp[i].qos_level_flip = pipe_ctx->ttu_regs.qos_level_flip;
state->hubp[i].min_ttu_vblank = pipe_ctx->ttu_regs.min_ttu_vblank;
}
/* Capture HUBBUB programming state */
if (dc->res_pool->hubbub) {
/* Individual DET buffer sizes - software state variables that program DET registers */
for (i = 0; i < 4u && i < dc->res_pool->pipe_count; i++) {
uint32_t det_size = res_ctx->pipe_ctx[i].det_buffer_size_kb;
switch (i) {
case 0:
state->hubbub.det0_size = det_size;
break;
case 1:
state->hubbub.det1_size = det_size;
break;
case 2:
state->hubbub.det2_size = det_size;
break;
case 3:
state->hubbub.det3_size = det_size;
break;
}
}
/* Compression buffer configuration - software state that programs COMPBUF_SIZE register */
// TODO: Handle logic for legacy DCN pre-DCN401
state->hubbub.compbuf_size = context->bw_ctx.bw.dcn.arb_regs.compbuf_size;
}
/* Capture DPP programming state for each pipe */
for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
if (!pipe_ctx->stream)
continue;
state->dpp[i].dpp_clock_enable = (pipe_ctx->plane_res.dpp != NULL) ? 1 : 0;
if (pipe_ctx->plane_state && pipe_ctx->plane_res.scl_data.recout.width > 0) {
/* Access dscl_prog_data directly - this contains the actual software state used for register programming */
struct dscl_prog_data *dscl_data = &pipe_ctx->plane_res.scl_data.dscl_prog_data;
/* Recout (Rectangle of Interest) configuration - software state that programs RECOUT registers */
state->dpp[i].recout_start_x = dscl_data->recout.x;
state->dpp[i].recout_start_y = dscl_data->recout.y;
state->dpp[i].recout_width = dscl_data->recout.width;
state->dpp[i].recout_height = dscl_data->recout.height;
/* MPC (Multiple Pipe/Plane Combiner) size - software state that programs MPC_SIZE registers */
state->dpp[i].mpc_width = dscl_data->mpc_size.width;
state->dpp[i].mpc_height = dscl_data->mpc_size.height;
/* DSCL mode - software state that programs SCL_MODE registers */
state->dpp[i].dscl_mode = dscl_data->dscl_mode;
/* Scaler ratios - software state that programs scale ratio registers (use actual programmed ratios) */
state->dpp[i].horz_ratio_int = dscl_data->ratios.h_scale_ratio >> 19; // Extract integer part from programmed ratio
state->dpp[i].vert_ratio_int = dscl_data->ratios.v_scale_ratio >> 19; // Extract integer part from programmed ratio
/* Basic scaler taps - software state that programs tap control registers (use actual programmed taps) */
state->dpp[i].h_taps = dscl_data->taps.h_taps + 1; // dscl_prog_data.taps stores (taps - 1), so add 1 back
state->dpp[i].v_taps = dscl_data->taps.v_taps + 1; // dscl_prog_data.taps stores (taps - 1), so add 1 back
}
}
/* Capture essential clock state for underflow analysis */
if (dc->clk_mgr && dc->clk_mgr->clks.dispclk_khz > 0) {
/* Core display clocks affecting bandwidth and timing */
state->dccg.dispclk_khz = dc->clk_mgr->clks.dispclk_khz;
/* Per-pipe clock configuration - only capture what's essential */
for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
if (pipe_ctx->stream) {
/* Essential clocks that directly affect underflow risk */
state->dccg.dppclk_khz[i] = dc->clk_mgr->clks.dppclk_khz;
state->dccg.pixclk_khz[i] = pipe_ctx->stream->timing.pix_clk_100hz / 10;
state->dccg.dppclk_enable[i] = 1;
/* DP stream clock only for DP signals */
if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
state->dccg.dpstreamclk_enable[i] = 1;
} else {
state->dccg.dpstreamclk_enable[i] = 0;
}
} else {
/* Inactive pipe - no clocks */
state->dccg.dppclk_khz[i] = 0;
state->dccg.pixclk_khz[i] = 0;
state->dccg.dppclk_enable[i] = 0;
if (i < 4) {
state->dccg.dpstreamclk_enable[i] = 0;
}
}
}
/* DSC clock state - only when actually using DSC */
for (i = 0; i < max_pipes; i++) {
struct pipe_ctx *pipe_ctx = (i < dc->res_pool->pipe_count) ? &res_ctx->pipe_ctx[i] : NULL;
if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->timing.dsc_cfg.num_slices_h > 0) {
state->dccg.dscclk_khz[i] = 400000; /* Typical DSC clock frequency */
} else {
state->dccg.dscclk_khz[i] = 0;
}
}
/* SYMCLK32 LE Control - only the essential HPO state for underflow analysis */
for (i = 0; i < 2; i++) {
state->dccg.symclk32_le_enable[i] = 0; /* Default: disabled */
}
/* Check for active HPO usage that affects symclk32_le */
for (unsigned int pipe_idx = 0; pipe_idx < MAX_PIPES && pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {
struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[pipe_idx];
if (!pipe_ctx->stream)
continue;
/* HPO FRL (HDMI FRL) streams use symclk32_le */
if (pipe_ctx->stream_res.hpo_frl_stream_enc && pipe_ctx->link_res.hpo_frl_link_enc) {
int hpo_le_inst = pipe_ctx->link_res.hpo_frl_link_enc->inst;
if (hpo_le_inst >= 0 && hpo_le_inst < 2) {
state->dccg.symclk32_le_enable[hpo_le_inst] = 1;
}
}
}
}
/* Capture essential DSC configuration for underflow analysis */
for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
if (pipe_ctx->stream && pipe_ctx->stream->timing.dsc_cfg.num_slices_h > 0) {
/* DSC is enabled - capture essential configuration */
state->dsc[i].dsc_clock_enable = 1;
/* DSC configuration affecting bandwidth and timing */
struct dc_dsc_config *dsc_cfg = &pipe_ctx->stream->timing.dsc_cfg;
state->dsc[i].dsc_num_slices_h = dsc_cfg->num_slices_h;
state->dsc[i].dsc_num_slices_v = dsc_cfg->num_slices_v;
state->dsc[i].dsc_bits_per_pixel = dsc_cfg->bits_per_pixel;
/* OPP pipe source for DSC forwarding */
if (pipe_ctx->stream_res.opp) {
state->dsc[i].dscrm_dsc_forward_enable = 1;
state->dsc[i].dscrm_dsc_opp_pipe_source = pipe_ctx->stream_res.opp->inst;
} else {
state->dsc[i].dscrm_dsc_forward_enable = 0;
state->dsc[i].dscrm_dsc_opp_pipe_source = 0;
}
} else {
/* DSC not enabled - clear all fields */
memset(&state->dsc[i], 0, sizeof(state->dsc[i]));
}
}
/* Capture MPC programming state - comprehensive register field coverage */
for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
if (pipe_ctx->plane_state && pipe_ctx->stream) {
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
/* MPCC blending tree and mode control - capture actual blend configuration */
state->mpc.mpcc_mode[i] = (plane_state->cm.blend_func.type != TF_TYPE_BYPASS) ? 1 : 0;
state->mpc.mpcc_alpha_blend_mode[i] = plane_state->per_pixel_alpha ? 1 : 0;
state->mpc.mpcc_alpha_multiplied_mode[i] = plane_state->pre_multiplied_alpha ? 1 : 0;
state->mpc.mpcc_blnd_active_overlap_only[i] = 0; /* Default - no overlap restriction */
state->mpc.mpcc_global_alpha[i] = plane_state->global_alpha_value;
state->mpc.mpcc_global_gain[i] = plane_state->global_alpha ? 255 : 0;
state->mpc.mpcc_bg_bpc[i] = 8; /* Standard 8-bit background */
state->mpc.mpcc_bot_gain_mode[i] = 0; /* Standard gain mode */
/* MPCC blending tree connections - capture tree topology */
if (pipe_ctx->bottom_pipe) {
state->mpc.mpcc_bot_sel[i] = pipe_ctx->bottom_pipe->pipe_idx;
} else {
state->mpc.mpcc_bot_sel[i] = 0xF; /* No bottom connection */
}
state->mpc.mpcc_top_sel[i] = pipe_ctx->pipe_idx; /* This pipe's DPP ID */
/* MPCC output gamma control - capture gamma programming */
if (plane_state->gamma_correction.type != GAMMA_CS_TFM_1D && plane_state->gamma_correction.num_entries > 0) {
state->mpc.mpcc_ogam_mode[i] = 1; /* Gamma enabled */
state->mpc.mpcc_ogam_select[i] = 0; /* Bank A selection */
state->mpc.mpcc_ogam_pwl_disable[i] = 0; /* PWL enabled */
} else {
state->mpc.mpcc_ogam_mode[i] = 0; /* Bypass mode */
state->mpc.mpcc_ogam_select[i] = 0;
state->mpc.mpcc_ogam_pwl_disable[i] = 1; /* PWL disabled */
}
/* MPCC pipe assignment and operational status */
if (pipe_ctx->stream_res.opp) {
state->mpc.mpcc_opp_id[i] = pipe_ctx->stream_res.opp->inst;
} else {
state->mpc.mpcc_opp_id[i] = 0xF; /* No OPP assignment */
}
/* MPCC status indicators - active pipe state */
state->mpc.mpcc_idle[i] = 0; /* Active pipe - not idle */
state->mpc.mpcc_busy[i] = 1; /* Active pipe - busy processing */
} else {
/* Pipe not active - set disabled/idle state for all fields */
state->mpc.mpcc_mode[i] = 0;
state->mpc.mpcc_alpha_blend_mode[i] = 0;
state->mpc.mpcc_alpha_multiplied_mode[i] = 0;
state->mpc.mpcc_blnd_active_overlap_only[i] = 0;
state->mpc.mpcc_global_alpha[i] = 0;
state->mpc.mpcc_global_gain[i] = 0;
state->mpc.mpcc_bg_bpc[i] = 0;
state->mpc.mpcc_bot_gain_mode[i] = 0;
state->mpc.mpcc_bot_sel[i] = 0xF; /* No bottom connection */
state->mpc.mpcc_top_sel[i] = 0xF; /* No top connection */
state->mpc.mpcc_ogam_mode[i] = 0; /* Bypass */
state->mpc.mpcc_ogam_select[i] = 0;
state->mpc.mpcc_ogam_pwl_disable[i] = 1; /* PWL disabled */
state->mpc.mpcc_opp_id[i] = 0xF; /* No OPP assignment */
state->mpc.mpcc_idle[i] = 1; /* Idle */
state->mpc.mpcc_busy[i] = 0; /* Not busy */
}
}
/* Capture OPP programming state for each pipe - comprehensive register field coverage */
for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
if (!pipe_ctx->stream)
continue;
if (pipe_ctx->stream_res.opp) {
struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
/* OPP Pipe Control */
state->opp[i].opp_pipe_clock_enable = 1; /* Active pipe has clock enabled */
/* Display Pattern Generator (DPG) Control - 19 fields */
if (pipe_ctx->stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {
state->opp[i].dpg_enable = 1;
} else {
/* Video mode - DPG disabled */
state->opp[i].dpg_enable = 0;
}
/* Format Control (FMT) - 18 fields */
state->opp[i].fmt_pixel_encoding = timing->pixel_encoding;
/* Chroma subsampling mode based on pixel encoding */
if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
state->opp[i].fmt_subsampling_mode = 1; /* 4:2:0 subsampling */
} else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
state->opp[i].fmt_subsampling_mode = 2; /* 4:2:2 subsampling */
} else {
state->opp[i].fmt_subsampling_mode = 0; /* No subsampling (4:4:4) */
}
state->opp[i].fmt_cbcr_bit_reduction_bypass = (timing->pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
state->opp[i].fmt_stereosync_override = (timing->timing_3d_format != TIMING_3D_FORMAT_NONE) ? 1 : 0;
/* Dithering control based on bit depth */
if (timing->display_color_depth < COLOR_DEPTH_121212) {
state->opp[i].fmt_spatial_dither_frame_counter_max = 15; /* Typical frame counter max */
state->opp[i].fmt_spatial_dither_frame_counter_bit_swap = 0; /* No bit swapping */
state->opp[i].fmt_spatial_dither_enable = 1;
state->opp[i].fmt_spatial_dither_mode = 0; /* Spatial dithering mode */
state->opp[i].fmt_spatial_dither_depth = timing->display_color_depth;
state->opp[i].fmt_temporal_dither_enable = 0; /* Spatial dithering preferred */
} else {
state->opp[i].fmt_spatial_dither_frame_counter_max = 0;
state->opp[i].fmt_spatial_dither_frame_counter_bit_swap = 0;
state->opp[i].fmt_spatial_dither_enable = 0;
state->opp[i].fmt_spatial_dither_mode = 0;
state->opp[i].fmt_spatial_dither_depth = 0;
state->opp[i].fmt_temporal_dither_enable = 0;
}
/* Truncation control for bit depth reduction */
if (timing->display_color_depth < COLOR_DEPTH_121212) {
state->opp[i].fmt_truncate_enable = 1;
state->opp[i].fmt_truncate_depth = timing->display_color_depth;
state->opp[i].fmt_truncate_mode = 0; /* Round mode */
} else {
state->opp[i].fmt_truncate_enable = 0;
state->opp[i].fmt_truncate_depth = 0;
state->opp[i].fmt_truncate_mode = 0;
}
/* Data clamping control */
state->opp[i].fmt_clamp_data_enable = 1; /* Clamping typically enabled */
state->opp[i].fmt_clamp_color_format = timing->pixel_encoding;
/* Dynamic expansion for limited range content */
if (timing->pixel_encoding != PIXEL_ENCODING_RGB) {
state->opp[i].fmt_dynamic_exp_enable = 1; /* YCbCr typically needs expansion */
state->opp[i].fmt_dynamic_exp_mode = 0; /* Standard expansion */
} else {
state->opp[i].fmt_dynamic_exp_enable = 0; /* RGB typically full range */
state->opp[i].fmt_dynamic_exp_mode = 0;
}
/* Legacy field for compatibility */
state->opp[i].fmt_bit_depth_control = timing->display_color_depth;
/* Output Buffer (OPPBUF) Control - 6 fields */
state->opp[i].oppbuf_active_width = timing->h_addressable;
state->opp[i].oppbuf_pixel_repetition = 0; /* No pixel repetition by default */
/* Multi-Stream Output (MSO) / ODM segmentation */
if (pipe_ctx->next_odm_pipe) {
state->opp[i].oppbuf_display_segmentation = 1; /* Segmented display */
state->opp[i].oppbuf_overlap_pixel_num = 0; /* ODM overlap pixels */
} else {
state->opp[i].oppbuf_display_segmentation = 0; /* Single segment */
state->opp[i].oppbuf_overlap_pixel_num = 0;
}
/* 3D/Stereo control */
if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE) {
state->opp[i].oppbuf_3d_vact_space1_size = 30; /* Typical stereo blanking */
state->opp[i].oppbuf_3d_vact_space2_size = 30;
} else {
state->opp[i].oppbuf_3d_vact_space1_size = 0;
state->opp[i].oppbuf_3d_vact_space2_size = 0;
}
/* DSC Forward Config - 3 fields */
if (timing->dsc_cfg.num_slices_h > 0) {
state->opp[i].dscrm_dsc_forward_enable = 1;
state->opp[i].dscrm_dsc_opp_pipe_source = pipe_ctx->stream_res.opp->inst;
state->opp[i].dscrm_dsc_forward_enable_status = 1; /* Status follows enable */
} else {
state->opp[i].dscrm_dsc_forward_enable = 0;
state->opp[i].dscrm_dsc_opp_pipe_source = 0;
state->opp[i].dscrm_dsc_forward_enable_status = 0;
}
} else {
/* No OPP resource - set all fields to disabled state */
memset(&state->opp[i], 0, sizeof(state->opp[i]));
}
}
/* Capture OPTC programming state for each pipe - comprehensive register field coverage */
for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
if (!pipe_ctx->stream)
continue;
if (pipe_ctx->stream_res.tg) {
struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
state->optc[i].otg_master_inst = pipe_ctx->stream_res.tg->inst;
/* OTG_CONTROL register - 5 fields */
state->optc[i].otg_master_enable = 1; /* Active stream */
state->optc[i].otg_disable_point_cntl = 0; /* Normal operation */
state->optc[i].otg_start_point_cntl = 0; /* Normal start */
state->optc[i].otg_field_number_cntl = (timing->flags.INTERLACE) ? 1 : 0;
state->optc[i].otg_out_mux = 0; /* Direct output */
/* OTG Horizontal Timing - 7 fields */
state->optc[i].otg_h_total = timing->h_total;
state->optc[i].otg_h_blank_start = timing->h_addressable;
state->optc[i].otg_h_blank_end = timing->h_total - timing->h_front_porch;
state->optc[i].otg_h_sync_start = timing->h_addressable + timing->h_front_porch;
state->optc[i].otg_h_sync_end = timing->h_addressable + timing->h_front_porch + timing->h_sync_width;
state->optc[i].otg_h_sync_polarity = timing->flags.HSYNC_POSITIVE_POLARITY ? 0 : 1;
state->optc[i].otg_h_timing_div_mode = (pipe_ctx->next_odm_pipe) ? 1 : 0; /* ODM divide mode */
/* OTG Vertical Timing - 7 fields */
state->optc[i].otg_v_total = timing->v_total;
state->optc[i].otg_v_blank_start = timing->v_addressable;
state->optc[i].otg_v_blank_end = timing->v_total - timing->v_front_porch;
state->optc[i].otg_v_sync_start = timing->v_addressable + timing->v_front_porch;
state->optc[i].otg_v_sync_end = timing->v_addressable + timing->v_front_porch + timing->v_sync_width;
state->optc[i].otg_v_sync_polarity = timing->flags.VSYNC_POSITIVE_POLARITY ? 0 : 1;
state->optc[i].otg_v_sync_mode = 0; /* Normal sync mode */
/* Initialize remaining core fields with appropriate defaults */
// TODO: Update logic for accurate vtotal min/max
state->optc[i].otg_v_total_max = timing->v_total + 100; /* Typical DRR range */
state->optc[i].otg_v_total_min = timing->v_total - 50;
state->optc[i].otg_v_total_mid = timing->v_total;
/* ODM configuration */
// TODO: Update logic to have complete ODM mappings (e.g. 3:1 and 4:1) stored in single pipe
if (pipe_ctx->next_odm_pipe) {
state->optc[i].optc_seg0_src_sel = pipe_ctx->stream_res.opp ? pipe_ctx->stream_res.opp->inst : 0;
state->optc[i].optc_seg1_src_sel = pipe_ctx->next_odm_pipe->stream_res.opp ? pipe_ctx->next_odm_pipe->stream_res.opp->inst : 0;
state->optc[i].optc_num_of_input_segment = 1; /* 2 segments - 1 */
} else {
state->optc[i].optc_seg0_src_sel = pipe_ctx->stream_res.opp ? pipe_ctx->stream_res.opp->inst : 0;
state->optc[i].optc_seg1_src_sel = 0;
state->optc[i].optc_num_of_input_segment = 0; /* Single segment */
}
/* DSC configuration */
if (timing->dsc_cfg.num_slices_h > 0) {
state->optc[i].optc_dsc_mode = 1; /* DSC enabled */
state->optc[i].optc_dsc_bytes_per_pixel = timing->dsc_cfg.bits_per_pixel / 16; /* Convert to bytes */
state->optc[i].optc_dsc_slice_width = timing->h_addressable / timing->dsc_cfg.num_slices_h;
} else {
state->optc[i].optc_dsc_mode = 0;
state->optc[i].optc_dsc_bytes_per_pixel = 0;
state->optc[i].optc_dsc_slice_width = 0;
}
/* Essential control fields */
state->optc[i].otg_stereo_enable = (timing->timing_3d_format != TIMING_3D_FORMAT_NONE) ? 1 : 0;
state->optc[i].otg_interlace_enable = timing->flags.INTERLACE ? 1 : 0;
state->optc[i].otg_clock_enable = 1; /* OTG clock enabled */
state->optc[i].vtg0_enable = 1; /* VTG enabled for timing generation */
/* Initialize other key fields to defaults */
state->optc[i].optc_input_pix_clk_en = 1;
state->optc[i].optc_segment_width = (pipe_ctx->next_odm_pipe) ? (timing->h_addressable / 2) : timing->h_addressable;
state->optc[i].otg_vready_offset = 1;
state->optc[i].otg_vstartup_start = timing->v_addressable + 10;
state->optc[i].otg_vupdate_offset = 0;
state->optc[i].otg_vupdate_width = 5;
} else {
/* No timing generator resource - initialize all fields to 0 */
memset(&state->optc[i], 0, sizeof(state->optc[i]));
}
}
state->state_valid = true;
return true;
}
void dc_log_preos_dmcub_info(const struct dc *dc)
{
dc_dmub_srv_log_preos_dmcub_info(dc->ctx->dmub_srv);
}
bool dc_get_qos_info(struct dc *dc, struct dc_qos_info *info)
{
const struct dc_clocks *clk = &dc->current_state->bw_ctx.bw.dcn.clk;
struct dc_requested_memory_qos requested = {};
memset(info, 0, sizeof(*info));
info->dcn_bandwidth_ub_in_mbps = (uint32_t)(clk->fclk_khz / 1000 * 64);
if (dc->clk_mgr && dc->clk_mgr->funcs->get_requested_memory_qos) {
dc->clk_mgr->funcs->get_requested_memory_qos(dc->clk_mgr, &requested);
info->qos_bandwidth_lb_in_mbps = requested.bandwidth_lb_in_mbps;
info->calculated_avg_bw_in_mbps = requested.calculated_avg_bw_in_mbps;
info->qos_max_latency_ub_in_ns = requested.max_latency_ub_in_ns;
info->qos_avg_latency_ub_in_ns = requested.avg_latency_ub_in_ns;
info->qos_max_bw_budget_in_mbps = requested.max_bw_budget_in_mbps;
}
return true;
}
unsigned int dc_override_memory_bandwidth_request(
struct dc *dc,
unsigned int bw_mbps)
{
if (!dc->clk_mgr || !dc->clk_mgr->funcs)
return 0;
return dc->clk_mgr->funcs->override_memory_bandwidth_request(
dc->clk_mgr, bw_mbps * 1000) / 1000;
}
static bool update_planes_and_stream_prepare_v2(
struct dc_update_scratch_space *scratch
)
{
// v2 is too tangled to break into stages, so just execute everything under lock
dc_exit_ips_for_hw_access(scratch->dc);
return update_planes_and_stream_v2(
scratch->dc,
scratch->surface_updates,
scratch->surface_count,
scratch->stream,
scratch->stream_update
);
}
static void update_planes_and_stream_execute_v2(
const struct dc_update_scratch_space *scratch
)
{
// Nothing to do, see `update_planes_and_stream_prepare_v2`
(void) scratch;
}
static bool update_planes_and_stream_cleanup_v2(
const struct dc_update_scratch_space *scratch
)
{
if (scratch->do_clear_update_bits)
clear_update_bits(scratch->surface_updates, scratch->surface_count, scratch->stream);
return false;
}
static void update_planes_and_stream_cleanup_v3_release_minimal(
struct dc_update_scratch_space *scratch,
bool backup
);
static bool update_planes_and_stream_prepare_v3_intermediate_seamless(
struct dc_update_scratch_space *scratch
)
{
return is_pipe_topology_transition_seamless_with_intermediate_step(
scratch->dc,
scratch->dc->current_state,
scratch->intermediate_context,
scratch->new_context
);
}
static void transition_countdown_init(struct dc *dc)
{
dc->check_config.transition_countdown_to_steady_state =
dc->debug.num_fast_flips_to_steady_state_override ?
dc->debug.num_fast_flips_to_steady_state_override :
NUM_FAST_FLIPS_TO_STEADY_STATE;
}
static bool update_planes_and_stream_prepare_v3(
struct dc_update_scratch_space *scratch
)
{
if (scratch->flow == UPDATE_V3_FLOW_NEW_CONTEXT_SEAMLESS) {
return true;
}
ASSERT(scratch->flow == UPDATE_V3_FLOW_INVALID);
dc_exit_ips_for_hw_access(scratch->dc);
/* HWSS path determination needs to be done prior to updating the surface and stream states. */
struct dc_fast_update fast_update[MAX_SURFACES] = { 0 };
populate_fast_updates(fast_update,
scratch->surface_updates,
scratch->surface_count,
scratch->stream_update);
const bool is_hwss_fast_path_only =
fast_update_only(scratch->dc,
fast_update,
scratch->surface_updates,
scratch->surface_count,
scratch->stream_update,
scratch->stream) &&
!scratch->dc->check_config.enable_legacy_fast_update;
if (!update_planes_and_stream_state(
scratch->dc,
scratch->surface_updates,
scratch->surface_count,
scratch->stream,
scratch->stream_update,
&scratch->update_type,
&scratch->new_context
)) {
return false;
}
if (scratch->new_context == scratch->dc->current_state) {
ASSERT(scratch->update_type < UPDATE_TYPE_FULL);
scratch->flow = is_hwss_fast_path_only
? UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FAST
: UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FULL;
return true;
}
ASSERT(scratch->update_type >= UPDATE_TYPE_FULL);
const bool seamless = scratch->dc->hwss.is_pipe_topology_transition_seamless(
scratch->dc,
scratch->dc->current_state,
scratch->new_context
);
if (seamless) {
scratch->flow = UPDATE_V3_FLOW_NEW_CONTEXT_SEAMLESS;
if (scratch->dc->check_config.deferred_transition_state)
/* reset countdown as steady state not reached */
transition_countdown_init(scratch->dc);
return true;
}
if (!scratch->dc->debug.disable_deferred_minimal_transitions) {
scratch->dc->check_config.deferred_transition_state = true;
transition_countdown_init(scratch->dc);
}
scratch->intermediate_context = create_minimal_transition_state(
scratch->dc,
scratch->new_context,
&scratch->intermediate_policy
);
if (scratch->intermediate_context) {
if (update_planes_and_stream_prepare_v3_intermediate_seamless(scratch)) {
scratch->flow = UPDATE_V3_FLOW_NEW_CONTEXT_MINIMAL_NEW;
return true;
}
update_planes_and_stream_cleanup_v3_release_minimal(scratch, false);
}
scratch->backup_context = scratch->dc->current_state;
restore_planes_and_stream_state(&scratch->dc->scratch.current_state, scratch->stream);
dc_state_retain(scratch->backup_context);
scratch->intermediate_context = create_minimal_transition_state(
scratch->dc,
scratch->backup_context,
&scratch->intermediate_policy
);
if (scratch->intermediate_context) {
if (update_planes_and_stream_prepare_v3_intermediate_seamless(scratch)) {
scratch->flow = UPDATE_V3_FLOW_NEW_CONTEXT_MINIMAL_CURRENT;
scratch->intermediate_count = initialize_empty_surface_updates(
scratch->stream, scratch->intermediate_updates
);
return true;
}
update_planes_and_stream_cleanup_v3_release_minimal(scratch, true);
}
scratch->flow = UPDATE_V3_FLOW_INVALID;
dc_state_release(scratch->backup_context);
restore_planes_and_stream_state(&scratch->dc->scratch.new_state, scratch->stream);
return false;
}
/**
* should_commit_intermediate_context - Does this flow commit a transient
* minimal-transition intermediate context
* @flow: the commit flow selected for this iteration
*
* Return: true if this iteration commits the intermediate context.
*/
static bool should_commit_intermediate_context(enum update_v3_flow flow)
{
return flow == UPDATE_V3_FLOW_NEW_CONTEXT_MINIMAL_NEW
|| flow == UPDATE_V3_FLOW_NEW_CONTEXT_MINIMAL_CURRENT;
}
static void update_planes_and_stream_execute_v3_commit(
const struct dc_update_scratch_space *scratch,
bool intermediate_update,
bool intermediate_context,
bool use_stream_update
)
{
commit_planes_for_stream(
scratch->dc,
intermediate_update ? scratch->intermediate_updates : scratch->surface_updates,
intermediate_update ? scratch->intermediate_count : scratch->surface_count,
scratch->stream,
use_stream_update ? scratch->stream_update : NULL,
intermediate_context ? UPDATE_TYPE_FULL : scratch->update_type,
// `dc->current_state` only used in `NO_NEW_CONTEXT`, where it is equal to `new_context`
intermediate_context ? scratch->intermediate_context : scratch->new_context
);
}
static void update_planes_and_stream_execute_v3(
const struct dc_update_scratch_space *scratch
)
{
bool intermediate_context = should_commit_intermediate_context(scratch->flow);
switch (scratch->flow) {
case UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FAST:
commit_planes_for_stream_fast(
scratch->dc,
scratch->surface_updates,
scratch->surface_count,
scratch->stream,
scratch->stream_update,
scratch->update_type,
scratch->new_context
);
break;
case UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FULL:
case UPDATE_V3_FLOW_NEW_CONTEXT_SEAMLESS:
update_planes_and_stream_execute_v3_commit(scratch, false, intermediate_context, true);
break;
case UPDATE_V3_FLOW_NEW_CONTEXT_MINIMAL_NEW:
update_planes_and_stream_execute_v3_commit(scratch, false, intermediate_context,
scratch->dc->check_config.deferred_transition_state);
break;
case UPDATE_V3_FLOW_NEW_CONTEXT_MINIMAL_CURRENT:
update_planes_and_stream_execute_v3_commit(scratch, true, intermediate_context, false);
break;
case UPDATE_V3_FLOW_INVALID:
default:
ASSERT(false);
}
}
static void update_planes_and_stream_cleanup_v3_release_minimal(
struct dc_update_scratch_space *scratch,
bool backup
)
{
release_minimal_transition_state(
scratch->dc,
scratch->intermediate_context,
backup ? scratch->backup_context : scratch->new_context,
&scratch->intermediate_policy
);
}
static void update_planes_and_stream_cleanup_v3_intermediate(
struct dc_update_scratch_space *scratch,
bool backup
)
{
swap_and_release_current_context(scratch->dc, scratch->intermediate_context, scratch->stream);
dc_state_retain(scratch->dc->current_state);
update_planes_and_stream_cleanup_v3_release_minimal(scratch, backup);
}
static bool update_planes_and_stream_cleanup_v3(
struct dc_update_scratch_space *scratch
)
{
switch (scratch->flow) {
case UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FAST:
case UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FULL:
if (scratch->dc->check_config.transition_countdown_to_steady_state)
scratch->dc->check_config.transition_countdown_to_steady_state--;
break;
case UPDATE_V3_FLOW_NEW_CONTEXT_SEAMLESS:
swap_and_release_current_context(scratch->dc, scratch->new_context, scratch->stream);
break;
case UPDATE_V3_FLOW_NEW_CONTEXT_MINIMAL_NEW:
update_planes_and_stream_cleanup_v3_intermediate(scratch, false);
if (scratch->dc->check_config.deferred_transition_state) {
dc_state_release(scratch->new_context);
} else {
scratch->flow = UPDATE_V3_FLOW_NEW_CONTEXT_SEAMLESS;
return true;
}
break;
case UPDATE_V3_FLOW_NEW_CONTEXT_MINIMAL_CURRENT:
update_planes_and_stream_cleanup_v3_intermediate(scratch, true);
dc_state_release(scratch->backup_context);
restore_planes_and_stream_state(&scratch->dc->scratch.new_state, scratch->stream);
scratch->flow = UPDATE_V3_FLOW_NEW_CONTEXT_SEAMLESS;
return true;
case UPDATE_V3_FLOW_INVALID:
default:
ASSERT(false);
}
if (scratch->do_clear_update_bits)
clear_update_bits(scratch->surface_updates, scratch->surface_count, scratch->stream);
return false;
}
struct dc_update_scratch_space *dc_update_state_init(
struct dc *dc,
const struct dc_state_update *updates
)
{
const enum dce_version version = dc->ctx->dce_version;
struct dc_update_scratch_space *scratch = dc_update_scratch_acquire(dc);
const bool has_stream_or_plane = updates->stream || updates->stream_update || updates->surface_updates;
const bool has_probe = updates->probe_updates;
const bool surface_without_stream = updates->surface_updates && !updates->stream;
const bool stream_update_without_stream = updates->stream_update && !updates->stream;
const bool bad_surface_count = updates->surface_count > 0 && !updates->surface_updates;
if (!scratch)
return NULL;
if (!has_stream_or_plane && !has_probe) {
dc_update_scratch_release(dc, scratch);
return NULL;
}
if (surface_without_stream || stream_update_without_stream || bad_surface_count) {
dc_update_scratch_release(dc, scratch);
return NULL;
}
*scratch = (struct dc_update_scratch_space){
.dc = dc,
.surface_updates = updates->surface_updates,
.surface_count = updates->surface_count,
.stream = updates->stream,
.stream_update = updates->stream_update,
.probe_updates = updates->probe_updates,
.update_v3 = version >= DCN_VERSION_4_01
|| version == DCN_VERSION_3_2
|| version == DCN_VERSION_3_21,
.do_clear_update_bits = version >= DCN_VERSION_1_0,
.new_context = NULL,
.flow = UPDATE_V3_FLOW_INVALID,
};
return scratch;
}
/**
* dc_update_probes_prepare - Commit the desired probe set into new_context.
* @scratch: commit scratch carrying the probe updates
*
* Return: true on success or when there is nothing to do; false when the
* desired set is unachievable.
*/
static bool dc_update_probes_prepare(struct dc_update_scratch_space *scratch)
{
struct dc *dc = scratch->dc;
const struct dc_probe_updates *probe_updates = scratch->probe_updates;
uint8_t i;
if (!probe_updates)
return true;
if (resource_validate_probe_set(dc, probe_updates->probes,
(uint8_t)probe_updates->probe_count) != DC_OK)
return false;
if (!scratch->new_context)
scratch->new_context = dc->current_state;
for (i = 0; i < probe_updates->probe_count && i < MAX_PROBES; i++)
scratch->new_context->probes[i] = probe_updates->probes[i];
scratch->new_context->probe_count = probe_updates->probe_count;
return true;
}
/**
* dc_update_probes_execute - Program the committed probes.
* @scratch: commit scratch carrying the probe updates
*
*/
static void dc_update_probes_execute(const struct dc_update_scratch_space *scratch)
{
struct dc *dc = scratch->dc;
if (should_commit_intermediate_context(scratch->flow))
return;
if (dc->hwss.program_perfmon)
dc->hwss.program_perfmon(dc, scratch->new_context);
}
bool dc_update_state_prepare(struct dc_update_scratch_space *scratch)
{
if (scratch->stream) {
bool ok = scratch->update_v3
? update_planes_and_stream_prepare_v3(scratch)
: update_planes_and_stream_prepare_v2(scratch);
if (!ok)
goto release_scratch;
}
if (!dc_update_probes_prepare(scratch))
goto release_scratch;
return true;
release_scratch:
/* execute and cleanup never run on this path, so release here. */
dc_update_scratch_release(scratch->dc, scratch);
return false;
}
void dc_update_state_execute(
const struct dc_update_scratch_space *scratch
)
{
if (scratch->stream)
scratch->update_v3
? update_planes_and_stream_execute_v3(scratch)
: update_planes_and_stream_execute_v2(scratch);
if (scratch->probe_updates)
dc_update_probes_execute(scratch);
}
bool dc_update_state_cleanup(
struct dc_update_scratch_space *scratch
)
{
bool more = false;
if (scratch->stream)
more = scratch->update_v3
? update_planes_and_stream_cleanup_v3(scratch)
: update_planes_and_stream_cleanup_v2(scratch);
if (!more)
dc_update_scratch_release(scratch->dc, scratch);
return more;
}
