Defined in 1 files as a prototype:
Defined in 1 files as a function:
Referenced in 13 files:
- drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c, line 762
- drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c, line 115
- drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c, line 107
- drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c, line 118
- drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c, line 125
- drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c, line 121
- drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c, line 127
- drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c, line 130
- drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c, line 138
- drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c, line 148
- drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c, line 137
- drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c, line 135
- drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c, line 137
Smatch caller information:
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn20/dcn20_hwseq.c dcn20_disable_pixel_data() -> dcn20_blank_pixel_data()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->clk_mgr | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->clk_mgr->bw_params | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->clk_mgr->funcs->set_max_memclk | 0,2269521457975533568,8712651765657735168 |
| PARAM_VALUE | 0 | dc->clk_mgr->funcs->set_min_memclk | 0,4489829976879345664,5857935723129503744 |
| PARAM_VALUE | 0 | dc->config.dc_mode_clk_limit_support | 1 |
| PARAM_VALUE | 0 | dc->current_state->res_ctx.pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->pipe_count | 1-u32max |
| PARAM_VALUE | 1 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream | 1-u64max |
| CAPPED_DATA | 0 | dc->clk_mgr->bw_params->clk_table.num_entries | 1 |
| CAPPED_DATA | 0 | dc->res_pool->pipe_count | 1 |
| DATA_SOURCE | 0 | dc | $0 |
| DATA_SOURCE | 1 | pipe_ctx | $1 |
| DATA_SOURCE | 2 | blank | $2 |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c disable_dangling_plane() -> (struct hwseq_private_funcs)->blank_pixel_data()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->current_state | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->current_state->bw_ctx.dml.vba.DPPCLKUsingSingleDPPChroma | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | dc->current_state->bw_ctx.dml.vba.DPPCLKUsingSingleDPPLuma | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | dc->current_state->res_ctx.pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq->funcs.blank_pixel_data | 1-u64max |
| PARAM_VALUE | 0 | dc->res_pool | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->funcs->prepare_mcache_programming | 0,804463396097511424,929829862513430528,8759039014133256192 |
| PARAM_VALUE | 0 | dc->res_pool->pipe_count | 1-u32max |
| PARAM_VALUE | 1 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg->funcs->enable_crtc | 0,4096-ptr_max |
| PARAM_VALUE | 2 | blank | 1 |
| DATA_SOURCE | 0 | dc | $0 |
| CONTAINER | 0 | -104-56-219720+0 | $(-1) |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn10/dcn10_hwseq.c dcn10_program_pipe() -> (struct hwseq_private_funcs)->blank_pixel_data()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->current_state | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->force_pstate_change_control | 0,2796816337411768320 |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->program_det_segments | 0,440092313918779392 |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->program_det_size | 0,3324494803509547008,8166695353123938304 |
| PARAM_VALUE | 0 | dc->res_pool->mpc->funcs->get_mpcc_for_dpp_from_secondary | 0 |
| PARAM_VALUE | 0 | dc->res_pool->mpc->funcs->remove_mpcc_from_secondary | 0 |
| PARAM_VALUE | 0 | dc->res_pool->pipe_count | 1-u32max |
| PARAM_VALUE | 0 | dc->res_pool->res_cap->num_dwb | 0-1 |
| PARAM_VALUE | 1 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->degamma_params.rgb_resulted->delta_blue_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->degamma_params.rgb_resulted->delta_green_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->degamma_params.rgb_resulted->delta_red_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->regamma_params.rgb_resulted->delta_blue_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->regamma_params.rgb_resulted->delta_green_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->regamma_params.rgb_resulted->delta_red_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->shaper_params.rgb_resulted->delta_blue_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->shaper_params.rgb_resulted->delta_green_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->shaper_params.rgb_resulted->delta_red_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.hubp->funcs->hubp_wait_pipe_read_start | 0,8092735316039704576 |
| PARAM_VALUE | 1 | pipe_ctx->plane_state | 0,4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe | 0 |
| CAPPED_DATA | 0 | dc->res_pool->pipe_count | 1 |
| DATA_SOURCE | 0 | dc | $0 |
| DATA_SOURCE | 1 | pipe_ctx | $1 |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn20/dcn20_hwseq.c dcn20_enable_stream_timing() -> (struct hwseq_private_funcs)->blank_pixel_data()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->current_state->res_ctx.pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->fbc_compressor->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->link_srv | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->dccg | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->dccg->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->dccg->funcs->dccg_init | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->dccg->funcs->set_dtbclk_p_src | 0,164379742607855616,963594910843088896,2241994770053472256,2682822004430630912,4094372161307451392 |
| PARAM_VALUE | 0 | dc->res_pool->dccg->funcs->set_pixel_rate_div | 0,960385507676274688,3545156886609068032,5703866155886583808,5992550597655154688,7657711864276148224 |
| PARAM_VALUE | 0 | dc->res_pool->mpc->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->mpc->funcs->set_out_rate_control | 0,3789993613906317312,3793505850180608000 |
| PARAM_VALUE | 0 | dc->res_pool->pipe_count | 1-u32max |
| PARAM_VALUE | 1 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->clock_source->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->dml_dlg_sys_param.deepsleep_dcfclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->dml_dlg_sys_param.mem_trip_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->dml_dlg_sys_param.t_extra_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->dml_dlg_sys_param.t_mclk_wm_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->dml_dlg_sys_param.t_sr_wm_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->dml_dlg_sys_param.t_urg_wm_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->dml_dlg_sys_param.total_flip_bw | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->dml_input.clks_cfg.dcfclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->dml_input.clks_cfg.dispclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->dml_input.clks_cfg.dppclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->dml_input.clks_cfg.refclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->dml_input.clks_cfg.socclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->dml_input.dout.output_bpp | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->dml_input.dout.wb.wb_hratio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->dml_input.dout.wb.wb_vratio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->dml_input.pipe.dest.pixel_rate_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->dml_input.pipe.scale_ratio_depth.hscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 1 | pipe_ctx->dml_input.pipe.scale_ratio_depth.hscl_ratio_c | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 1 | pipe_ctx->dml_input.pipe.scale_ratio_depth.vinit | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 1 | pipe_ctx->dml_input.pipe.scale_ratio_depth.vinit_bot | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 1 | pipe_ctx->dml_input.pipe.scale_ratio_depth.vinit_bot_c | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 1 | pipe_ctx->dml_input.pipe.scale_ratio_depth.vinit_c | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 1 | pipe_ctx->dml_input.pipe.scale_ratio_depth.vscl_ratio | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 1 | pipe_ctx->dml_input.pipe.scale_ratio_depth.vscl_ratio_c | -9.223372e+18-9.223372e+18 |
| PARAM_VALUE | 1 | pipe_ctx->dml_input.pipe.src.dcc_fraction_of_zs_req_chroma | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->dml_input.pipe.src.dcc_fraction_of_zs_req_luma | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->dml_input.pipe.src.xfc_params.xfc_tslv_vready_offset_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->dml_input.pipe.src.xfc_params.xfc_tslv_vupdate_offset_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->dml_input.pipe.src.xfc_params.xfc_tslv_vupdate_width_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->pipe_dlg_param.pixel_rate_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->stream | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream->apply_seamless_boot_optimization | 0 |
| PARAM_VALUE | 1 | pipe_ctx->stream->ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream->link | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.audio->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.audio->funcs->az_disable_hbr_audio | 5077894766283632640 |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.opp->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg->funcs->set_h_timing_div_manual_mode | 0,3943045918683873280,4412274745866633216,7210936702807244800 |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg->funcs->set_static_screen_control | 0,5071642371786563584,5913575906034724864,8835630547784204288 |
| PARAM_VALUE | 2 | blank | 1 |
| CAPPED_DATA | 0 | dc->res_pool->pipe_count | 1 |
| DATA_SOURCE | 0 | dc | $2 |
| DATA_SOURCE | 1 | pipe_ctx | $0 |
| NOCHECK_CALL | |||
| HOST_DATA | 1 | pipe_ctx->stream->link->panel_cntl->stored_backlight_registers.BL_PWM_CNTL | 0-u32max |
| HOST_DATA | 1 | pipe_ctx->stream->link->panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 | 0-u32max |
| HOST_DATA | 1 | pipe_ctx->stream->link->panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL | 0-u32max |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn20/dcn20_hwseq.c dcn20_program_front_end_for_ctx() -> (struct hwseq_private_funcs)->blank_pixel_data()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->current_state | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->current_state->res_ctx.pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq->funcs.blank_pixel_data | 1-u64max |
| PARAM_VALUE | 0 | dc->res_pool | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->force_pstate_change_control | 0,2796816337411768320 |
| PARAM_VALUE | 0 | dc->res_pool->pipe_count | 1-u32max |
| PARAM_VALUE | 1 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 2 | blank | 1 |
| CAPPED_DATA | 0 | dc->res_pool->pipe_count | 1 |
| DATA_SOURCE | 0 | dc | $0 |
| CONTAINER | 0 | -104-56-219720+0 | $(-1) |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn20/dcn20_hwseq.c dcn20_program_front_end_for_ctx() -> (struct hwseq_private_funcs)->blank_pixel_data()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->current_state | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->force_pstate_change_control | 0,2796816337411768320 |
| PARAM_VALUE | 0 | dc->res_pool->pipe_count | 1-u32max |
| PARAM_VALUE | 1 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->prev_odm_pipe | 0 |
| PARAM_VALUE | 1 | pipe_ctx->stream | 1-u64max |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe | 0 |
| PARAM_VALUE | 2 | blank | 1 |
| CAPPED_DATA | 0 | dc->res_pool->pipe_count | 1 |
| DATA_SOURCE | 0 | dc | $0 |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn20/dcn20_hwseq.c dcn20_program_pipe() -> (struct hwseq_private_funcs)->blank_pixel_data()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->force_pstate_change_control | 0,2796816337411768320 |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->program_det_segments | 0,440092313918779392 |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->program_det_size | 0,3324494803509547008,8166695353123938304 |
| PARAM_VALUE | 0 | dc->res_pool->pipe_count | 1-u32max |
| PARAM_VALUE | 0 | dc->res_pool->res_cap->num_dwb | 0-1 |
| PARAM_VALUE | 1 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->degamma_params.rgb_resulted->delta_blue_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->degamma_params.rgb_resulted->delta_green_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->degamma_params.rgb_resulted->delta_red_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->regamma_params.rgb_resulted->delta_blue_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->regamma_params.rgb_resulted->delta_green_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->regamma_params.rgb_resulted->delta_red_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->shaper_params.rgb_resulted->delta_blue_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->shaper_params.rgb_resulted->delta_green_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->shaper_params.rgb_resulted->delta_red_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.hubp->funcs->hubp_wait_pipe_read_start | 0,8092735316039704576 |
| PARAM_VALUE | 1 | pipe_ctx->plane_state | 0,4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->prev_odm_pipe | 0 |
| PARAM_VALUE | 1 | pipe_ctx->stream | 1-u64max |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe | 0 |
| DATA_SOURCE | 0 | dc | $0 |
| DATA_SOURCE | 1 | pipe_ctx | $1 |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn20/dcn20_hwseq.c dcn20_update_bandwidth() -> (struct hwseq_private_funcs)->blank_pixel_data()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->pipe_count | 1-u32max |
| PARAM_VALUE | 1 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->plane_state | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->prev_odm_pipe | 0 |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe | 0 |
| DATA_SOURCE | 0 | dc | $0 |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn401/dcn401_hwseq.c dcn401_enable_stream_timing() -> (struct hwseq_private_funcs)->blank_pixel_data()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->current_state->res_ctx.pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->fbc_compressor->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->link_srv | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->dccg | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->dccg->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->dccg->funcs->set_dtbclk_p_src | 0,164379742607855616,963594910843088896,2241994770053472256,2682822004430630912,4094372161307451392 |
| PARAM_VALUE | 0 | dc->res_pool->dccg->funcs->set_pixel_rate_div | 0,960385507676274688,3545156886609068032,5703866155886583808,5992550597655154688,7657711864276148224 |
| PARAM_VALUE | 0 | dc->res_pool->pipe_count | 1-u32max |
| PARAM_VALUE | 1 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->clock_source->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream->apply_seamless_boot_optimization | 0 |
| PARAM_VALUE | 1 | pipe_ctx->stream->ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream->link | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg | 1 |
| PARAM_VALUE | 1 | pipe_ctx->stream->link->phy_state.symclk_state | 0-2 |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.audio->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.audio->funcs->az_disable_hbr_audio | 5077894766283632640 |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.opp | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.opp->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg->funcs->set_h_timing_div_manual_mode | 0,3943045918683873280,4412274745866633216,7210936702807244800 |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg->funcs->set_static_screen_control | 0,5071642371786563584,5913575906034724864,8835630547784204288 |
| PARAM_VALUE | 2 | blank | 1 |
| CAPPED_DATA | 0 | dc->res_pool->pipe_count | 1 |
| DATA_SOURCE | 0 | dc | $2 |
| DATA_SOURCE | 1 | pipe_ctx | $0 |
| NOCHECK_CALL | |||
| HOST_DATA | 1 | pipe_ctx->stream->link->panel_cntl->stored_backlight_registers.BL_PWM_CNTL | 0-u32max |
| HOST_DATA | 1 | pipe_ctx->stream->link->panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 | 0-u32max |
| HOST_DATA | 1 | pipe_ctx->stream->link->panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL | 0-u32max |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn401/dcn401_hwseq.c dcn401_program_front_end_for_ctx() -> (struct hwseq_private_funcs)->blank_pixel_data()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->current_state | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->current_state->res_ctx.pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->debug.enable_block_sequence_programming | 0 |
| PARAM_VALUE | 0 | dc->hwseq | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq->funcs.blank_pixel_data | 1-u64max |
| PARAM_VALUE | 0 | dc->res_pool | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->force_pstate_change_control | 0,2796816337411768320 |
| PARAM_VALUE | 0 | dc->res_pool->pipe_count | 1-u32max |
| PARAM_VALUE | 1 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 2 | blank | 1 |
| CAPPED_DATA | 0 | dc->res_pool->pipe_count | 1 |
| DATA_SOURCE | 0 | dc | $0 |
| CONTAINER | 0 | -104-56-219720+0 | $(-1) |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn401/dcn401_hwseq.c dcn401_program_front_end_for_ctx() -> (struct hwseq_private_funcs)->blank_pixel_data()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->current_state | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->debug.enable_block_sequence_programming | 0 |
| PARAM_VALUE | 0 | dc->res_pool | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->force_pstate_change_control | 0,2796816337411768320 |
| PARAM_VALUE | 0 | dc->res_pool->pipe_count | 1-u32max |
| PARAM_VALUE | 1 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->prev_odm_pipe | 0 |
| PARAM_VALUE | 1 | pipe_ctx->stream | 1-u64max |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe | 0 |
| PARAM_VALUE | 2 | blank | 1 |
| CAPPED_DATA | 0 | dc->res_pool->pipe_count | 1 |
| DATA_SOURCE | 0 | dc | $0 |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn401/dcn401_hwseq.c dcn401_program_pipe() -> (struct hwseq_private_funcs)->blank_pixel_data()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->hubbub | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->force_pstate_change_control | 0,2796816337411768320 |
| PARAM_VALUE | 0 | dc->res_pool->pipe_count | 1-u32max |
| PARAM_VALUE | 1 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->degamma_params.rgb_resulted->delta_blue_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->degamma_params.rgb_resulted->delta_green_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->degamma_params.rgb_resulted->delta_red_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->regamma_params.rgb_resulted->delta_blue_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->regamma_params.rgb_resulted->delta_green_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->regamma_params.rgb_resulted->delta_red_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->shaper_params.rgb_resulted->delta_blue_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->shaper_params.rgb_resulted->delta_green_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.dpp->shaper_params.rgb_resulted->delta_red_reg | 0-4294967295 |
| PARAM_VALUE | 1 | pipe_ctx->plane_state | 0,4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->prev_odm_pipe | 0 |
| PARAM_VALUE | 1 | pipe_ctx->stream | 1-u64max |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe | 0 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_dlg_sys_param.deepsleep_dcfclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_dlg_sys_param.mem_trip_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_dlg_sys_param.t_extra_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_dlg_sys_param.t_mclk_wm_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_dlg_sys_param.t_sr_wm_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_dlg_sys_param.t_urg_wm_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_dlg_sys_param.total_flip_bw | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_input.clks_cfg.dcfclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_input.clks_cfg.dispclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_input.clks_cfg.dppclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_input.clks_cfg.refclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_input.clks_cfg.socclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_input.dout.output_bpp | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_input.dout.wb.wb_hratio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_input.dout.wb.wb_vratio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_input.pipe.dest.pixel_rate_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_input.pipe.scale_ratio_depth.hscl_ratio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_input.pipe.scale_ratio_depth.hscl_ratio_c | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_input.pipe.scale_ratio_depth.vinit | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_input.pipe.scale_ratio_depth.vinit_bot | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_input.pipe.scale_ratio_depth.vinit_bot_c | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_input.pipe.scale_ratio_depth.vinit_c | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_input.pipe.scale_ratio_depth.vscl_ratio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_input.pipe.scale_ratio_depth.vscl_ratio_c | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_input.pipe.src.dcc_fraction_of_zs_req_chroma | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_input.pipe.src.dcc_fraction_of_zs_req_luma | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_input.pipe.src.xfc_params.xfc_tslv_vready_offset_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_input.pipe.src.xfc_params.xfc_tslv_vupdate_offset_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->dml_input.pipe.src.xfc_params.xfc_tslv_vupdate_width_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->pipe_dlg_param.pixel_rate_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe->top_pipe | 0 |
| DATA_SOURCE | 0 | dc | $0 |
| DATA_SOURCE | 1 | pipe_ctx | $1 |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn401/dcn401_hwseq.c dcn401_update_bandwidth() -> (struct hwseq_private_funcs)->blank_pixel_data()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->pipe_count | 1-u32max |
| PARAM_VALUE | 1 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->plane_state | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->prev_odm_pipe | 0 |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->top_pipe | 0 |
| DATA_SOURCE | 0 | dc | $0 |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn401/dcn401_hwseq.c dcn401_update_odm() -> (struct hwseq_private_funcs)->blank_pixel_data()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->funcs->prepare_mcache_programming | 0,804463396097511424,929829862513430528,8759039014133256192 |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->force_pstate_change_control | 0,2796816337411768320 |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->program_det_segments | 0,440092313918779392 |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->program_det_size | 0,3324494803509547008,8166695353123938304 |
| PARAM_VALUE | 0 | dc->res_pool->mpc->funcs->get_mpcc_for_dpp_from_secondary | 0 |
| PARAM_VALUE | 0 | dc->res_pool->mpc->funcs->remove_mpcc_from_secondary | 0 |
| PARAM_VALUE | 1 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_dlg_sys_param.deepsleep_dcfclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_dlg_sys_param.mem_trip_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_dlg_sys_param.t_extra_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_dlg_sys_param.t_mclk_wm_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_dlg_sys_param.t_sr_wm_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_dlg_sys_param.t_urg_wm_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_dlg_sys_param.total_flip_bw | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_input.clks_cfg.dcfclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_input.clks_cfg.dispclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_input.clks_cfg.dppclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_input.clks_cfg.refclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_input.clks_cfg.socclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_input.dout.output_bpp | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_input.dout.wb.wb_hratio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_input.dout.wb.wb_vratio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_input.pipe.dest.pixel_rate_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_input.pipe.src.dcc_fraction_of_zs_req_chroma | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->dml_input.pipe.src.dcc_fraction_of_zs_req_luma | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->next_odm_pipe->pipe_dlg_param.pixel_rate_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.hubp->funcs->hubp_wait_pipe_read_start | 0,8092735316039704576 |
| PARAM_VALUE | 1 | pipe_ctx->stream | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream->ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.dsc | 0,4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg->funcs->program_global_sync | 0,4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg->funcs->set_vtg_params | 0,4096-ptr_max |
| PARAM_VALUE | 2 | blank | 1 |
| DATA_SOURCE | 0 | dc | $0 |
| DATA_SOURCE | 1 | pipe_ctx | $2 |
| CONTAINER | 0 | -104-56-219720+0 | $(-1) |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn32/dcn32_hwseq.c dcn32_update_odm() -> (struct hwseq_private_funcs)->blank_pixel_data()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->funcs->prepare_mcache_programming | 0,804463396097511424,929829862513430528,8759039014133256192 |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->force_pstate_change_control | 0,2796816337411768320 |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->program_det_segments | 0,440092313918779392 |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->program_det_size | 0,3324494803509547008,8166695353123938304 |
| PARAM_VALUE | 0 | dc->res_pool->mpc->funcs->get_mpcc_for_dpp_from_secondary | 0 |
| PARAM_VALUE | 0 | dc->res_pool->mpc->funcs->remove_mpcc_from_secondary | 0 |
| PARAM_VALUE | 1 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->plane_res.hubp->funcs->hubp_wait_pipe_read_start | 0,8092735316039704576 |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.dsc | 0,4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg->funcs->program_global_sync | 0,4096-ptr_max |
| PARAM_VALUE | 1 | pipe_ctx->stream_res.tg->funcs->set_vtg_params | 0,4096-ptr_max |
| PARAM_VALUE | 2 | blank | 1 |
| DATA_SOURCE | 0 | dc | $0 |
| DATA_SOURCE | 1 | pipe_ctx | $2 |
| CONTAINER | 0 | -104-56-219720+0 | $(-1) |
| NOCHECK_CALL |