Defined in 1 files as a prototype:

Defined in 1 files as a function:

Referenced in 2 files:

Smatch caller information:

drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dpms.c link_set_dpms_off() -> link_set_dsc_enable()

Type Parameter Key Value
PARAM_VALUE 0 pipe_ctx 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->prev_odm_pipe 0
PARAM_VALUE 0 pipe_ctx->stream 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream->ctx 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream->ctx->dc 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream->link 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream->link->ctx 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream->link->ctx->dc->dml.vba.DPPCLKUsingSingleDPPChroma -1.797693e+308-1.797693e+308
PARAM_VALUE 0 pipe_ctx->stream->link->ctx->dc->dml.vba.DPPCLKUsingSingleDPPLuma -1.797693e+308-1.797693e+308
PARAM_VALUE 0 pipe_ctx->stream->link->ctx->dc->res_pool->dccg->funcs->enable_hdmicharclk 0,4,4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream->link->dc->hwseq->wa_state.skip_blank_stream 0-1
PARAM_VALUE 0 pipe_ctx->stream->link->panel_cntl->ctx->dmub_srv->dm 0-s64max
PARAM_VALUE 0 pipe_ctx->stream->link->phy_state.symclk_state 0,2
PARAM_VALUE 0 pipe_ctx->stream->link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->list.prev->next 5159360019465732096
PARAM_VALUE 0 pipe_ctx->stream->link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->list.prev->prev 5159360019465732096
PARAM_VALUE 0 pipe_ctx->stream->link->priv->dm_dp_aux.aux.hw_mutex.osq.tail.counter s32min-s32max
PARAM_VALUE 0 pipe_ctx->stream->signal 32,64,128
PARAM_VALUE 0 pipe_ctx->stream->sink 0,4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream->timing.flags.DSC 1
PARAM_VALUE 0 pipe_ctx->stream_res.audio->funcs->az_disable_hbr_audio 5077894766283632640
PARAM_VALUE 0 pipe_ctx->stream_res.tg->funcs->set_odm_bypass 0,1134321944835944448,1603183173331275776,6116399471158304768,7645597569047158784,8219396703655817216
PARAM_VALUE 0 pipe_ctx->stream_res.tg->funcs->set_static_screen_control 0,5071642371786563584,5913575906034724864,8835630547784204288
PARAM_VALUE 0 pipe_ctx->top_pipe 0
PARAM_VALUE 1 enable 0
CAPPED_DATA 0 pipe_ctx->stream->link 1
DATA_SOURCE 0 pipe_ctx $0
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dpms.c link_set_dpms_on_pre_enable_link() -> link_set_dsc_enable()

Type Parameter Key Value
PARAM_VALUE 0 pipe_ctx 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->prev_odm_pipe 0
PARAM_VALUE 0 pipe_ctx->stream 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream->ctx 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream->ctx->dc 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream->ctx->dc->res_pool 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream->ctx->dc->res_pool->funcs 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream->dpms_off 0
PARAM_VALUE 0 pipe_ctx->stream->signal 0-511,513-u32max
PARAM_VALUE 0 pipe_ctx->stream->sink 0,4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream_res.audio->funcs->az_disable_hbr_audio 5077894766283632640
PARAM_VALUE 0 pipe_ctx->stream_res.encoder_info_frame.avi->sb 0-255
PARAM_VALUE 0 pipe_ctx->stream_res.tg 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream_res.tg->funcs 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream_res.tg->funcs->set_out_mux 0,400365980042444800,1252548466178600960
PARAM_VALUE 0 pipe_ctx->stream_res.tg->funcs->set_static_screen_control 0,5071642371786563584,5913575906034724864,8835630547784204288
PARAM_VALUE 0 pipe_ctx->top_pipe 0
PARAM_VALUE 1 enable 1
DATA_SOURCE 0 pipe_ctx $1
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn60/dcn60_hwseq.c dcn60_apply_single_controller_ctx_to_hw() -> (struct link_service)->set_dsc_enable()

Type Parameter Key Value
PARAM_VALUE 0 pipe_ctx 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream->adjust.timing_adjust_pending 0
PARAM_VALUE 0 pipe_ctx->stream->link->priv->dm_dp_aux.aux.hw_mutex.dep_map->name 0-255
PARAM_VALUE 0 pipe_ctx->stream->signal 128
PARAM_VALUE 0 pipe_ctx->stream->timing.flags.DSC 1
PARAM_VALUE 0 pipe_ctx->stream_res.audio 0,4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream_res.audio->funcs 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream_res.audio->funcs->az_disable_hbr_audio 5077894766283632640
PARAM_VALUE 0 pipe_ctx->stream_res.opp 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream_res.opp->funcs 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream_res.stream_enc 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream_res.stream_enc->funcs 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream_res.tg 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream_res.tg->funcs 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream_res.tg->funcs->set_static_screen_control 0,5071642371786563584,5913575906034724864,8835630547784204288
PARAM_VALUE 1 enable 1
DATA_SOURCE 0 pipe_ctx $0
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dce110/dce110_hwseq.c dce110_apply_single_controller_ctx_to_hw() -> (struct link_service)->set_dsc_enable()

Type Parameter Key Value
PARAM_VALUE 0 pipe_ctx 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->prev_odm_pipe 0
PARAM_VALUE 0 pipe_ctx->stream 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream->adjust.timing_adjust_pending 0
PARAM_VALUE 0 pipe_ctx->stream->link 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream->link->priv->dm_dp_aux.aux.hw_mutex.dep_map->name 0-255
PARAM_VALUE 0 pipe_ctx->stream->signal 128
PARAM_VALUE 0 pipe_ctx->stream->timing.flags.DSC 1
PARAM_VALUE 0 pipe_ctx->stream_res.audio 0,4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream_res.audio->funcs 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream_res.audio->funcs->az_disable_hbr_audio 5077894766283632640
PARAM_VALUE 0 pipe_ctx->stream_res.opp 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream_res.opp->funcs 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream_res.stream_enc 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream_res.stream_enc->funcs 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream_res.tg 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream_res.tg->funcs 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream_res.tg->funcs->set_static_screen_control 0,5071642371786563584,5913575906034724864,8835630547784204288
PARAM_VALUE 0 pipe_ctx->top_pipe 0
PARAM_VALUE 1 enable 1
CAPPED_DATA 0 pipe_ctx->stream 1
DATA_SOURCE 0 pipe_ctx $0
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn31/dcn31_hwseq.c dcn31_reset_back_end_for_pipe() -> (struct link_service)->set_dsc_enable()

Type Parameter Key Value
PARAM_VALUE 0 pipe_ctx 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->prev_odm_pipe 0
PARAM_VALUE 0 pipe_ctx->stream 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream->adjust.timing_adjust_pending 0
PARAM_VALUE 0 pipe_ctx->stream->link 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream->link->ctx->dc->res_pool->dccg->funcs->enable_hdmicharclk 0,4,4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream->link->dc 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream->signal 128
PARAM_VALUE 0 pipe_ctx->stream->timing.flags.DSC 1
PARAM_VALUE 0 pipe_ctx->stream_res.stream_enc 1-u64max
PARAM_VALUE 0 pipe_ctx->stream_res.tg 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream_res.tg->funcs 4096-ptr_max
PARAM_VALUE 0 pipe_ctx->stream_res.tg->funcs->set_odm_bypass 0,1134321944835944448,1603183173331275776,6116399471158304768,7645597569047158784,8219396703655817216
PARAM_VALUE 0 pipe_ctx->top_pipe 0
PARAM_VALUE 1 enable 0
CAPPED_DATA 0 pipe_ctx->stream 1
DATA_SOURCE 0 pipe_ctx $1
NOCHECK_CALL